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es specifications august 11, 2003 revision 0.6 u ltra c hip the coolest lcd driver. ever!! 80 x 104rgb c-stn lcd controller-driver w/ 32-shade per dot, 12 -bit per rgb (dither 221k) h igh -v oltage m ixed -s ignal ic
uc1682 80x104rgb cstn controller-driver revision 0.6 1 t able of c ontent introduction ................................................................................................................ 1 main applications ....................................................................................................... 1 feature highlights.................................................................................................... 1 ordering information .............................................................................................. 2 block diagram ............................................................................................................. 4 pin description ............................................................................................................ 5 reference cog layout ............................................................................................ 9 command table.......................................................................................................... 13 command description ............................................................................................. 15 lcd voltage setting ............................................................................................... 29 v lcd quick reference............................................................................................... 30 lcd display controls............................................................................................. 32 host interface .......................................................................................................... 35 display data ram ...................................................................................................... 42 reset & power management ................................................................................ 45 absolute maximum ratings .................................................................................. 49 specifications............................................................................................................ 50 ac characteristics ................................................................................................. 51 physical dimensions................................................................................................ 58 alignment mark information.............................................................................. 59 pi information ............................................................................................................ 60 pad coordinates....................................................................................................... 61 tray information...................................................................................................... 65 cof information ........................................................................................................ 66 revision history........................................................................................................ 68
uc1682 80x104rgb cstn controller-driver revision 0.6 1 uc1682 single-chip, ultra-low power 80com x 312seg matrix passive color lcd controller-driver i ntroduction uc1682 is an advanced high-voltage mixed- signal cmos ic, especially designed for the display needs of ultra-low power hand-held devices. this chip employs ultrachip?s unique dcc (direct capacitor coupling) driver architecture to achieve near crosstalk free images, with well balanced gray shades and vivid colors. in addition to low power com and seg drivers, uc1682 contains all necessary circuits for high-v lcd power supply, bias voltage generation, timing generation and graphics data memory. advanced circuit design techniques are employed to minimize ex ternal component counts and reduce connector size while achieving extremely low power consumption. m ain a pplications ? cellular phones and other battery operated palm top devices or portable instruments f eature h ighlights ? single chip controller-driver for 80x104 matrix c-stn lcd with comprehensive support for input format and color depth: 8-bit rgb: 256 color 12-bit rgb: 4k color 16-bit rgb: 56k color (dithering) 24-bit rgb: 221k color (dithering) ? one software readable id pin to support configurable vender identification. ? partial scroll function and programmable data update window to support flexible manipulation of screen data. ? support both row ordered and column ordered display buffer ram access. ? support industry standard 3-wire, 4-wire serial bus (s9, s8, s8uc) and 8-bit/4-bit parallel bus (8080 or 6800). ? special driver structure and gray shade modulation scheme. ultra-low power consumption under all display patterns. ? fully programmable mux rate, partial display window, bias ratio and line rate allow many flexible power management options. ? software programmable frame rates up to 250hz. support the use of fast liquid crystal material for speedy lcd response. ? software programmable four temperature compensation coefficients. ? on-chip power-on reset and software reset command, make rst pin optional. ? self-configuring 10x charge pump with on- chip pumping capacitors. only 2/3 external capacitors are required to operate. ? flexible data addressing/mapping schemes to support wide ranges of software models and lcd layout placements. ? very low pin count (9~10 pins with s9) allows exceptional image quality in cog format on conventional ito glass. ? many on-chip and i/o pad layout features to support optimized cog applications. ? v dd (digital) range: 1.8v ~ 3.3v v dd (analog) range: 2.4v ~ 3.3v lcd v op range: 5.0v ~ 10.5v ? available otp v lcd trimming option to support precise lcd contrast matching ? available in cof and gold bump dies bump pitch: 41.5m bump gap: 17m bump surface: 3,000m 2
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 2 es specifications o rdering i nformation part number versions description uc1682xhcz gold bumped die with pi without otp option UC1682THCZ gold bumped die with pi with otp option uc1682xfbz cof without otp option uc1682tfbz cof with otp option convention note: grayed-out contents are functions not available yet.
uc1682 80x104rgb cstn controller-driver revision 0.6 3 general notes a pplication i nformation for improved readability, the specification contains many appl ication data points. when application information is given, it is advisory and does not form part of the specification for the device. b are d ie d isclaimer all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of ultrachip?s delivery. there is no post waffle saw/pack testing performed on individual die. although the latest processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, ultrachip has no control of third party procedures in the handling, packing or asse mbly of the die. accordingly, it is the responsibility of the customer to test and qualify their applications in which the die is to be used. ultrachip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. otp c ell l ight s ensitivity the otp memory cell is sensitive to photon excitation. under extended exposure to strong ambient light, the otp cells can lose its content before the specified memory retention time span. the system designer is advised to provide proper light shields to realize full otp content retention performance. l ife s upport a pplications these devices are not designed for use in life support applianc es, or systems where malfunction of these products can reasonably be expected to result in personal injuries. custom er using or selling these products for use in such applications do so at their own risk.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 4 es specifications b lock d iagram com drivers seg drivers power-on & reset control row address generator clock & timing gen. host interface control & status register command column address generator display data ram display data latches level shifters level shifter v lcd & bias generator page address generator data ram i/o buffer c l c b1 c b0
uc1682 80x104rgb cstn controller-driver revision 0.6 5 p in d escription name type pins description m ain p ower s upply v dd v dd2 v dd3 pwr v dd2 /v dd3 is the analog power supply and it should be connected to the same power source. v dd is the digital power supply and it should be connected to a voltage source that is no higher than v dd2 /v dd3 . please maintain the following relationship: v dd +1v v dd2/3 v dd . " minimize the trace resistance for v dd and v dd2 /v dd3 . v ss v ss2 gnd ground. connect v ss and v ss2 to the shared gnd pin. minimize the trace resistance for this node. lcd p ower s upply & v oltage c ontrol v bias i this is the reference voltage to generate the actual seg driving voltage. v bias can be used to fine tune v lcd by external variable resistors. internal resistor network has been prov ided to simplify external trimming circuit. the following network is sufficient for most applications. an internal rc filter is provided to filter noise on the v bias pin. when not used, it is ok to leave v bias open circuit. if noise starts to cause problem, connect a small bypass capacitor between v bias and v ss . in the otp version, this pin is di sconnected from internal circuit. so, there is no need to add bypass capacitor for this pin for otp version. v b1+ v b1? v b0+ v b0? pwr lcd bias voltages. these are the voltage sources to provide seg driving currents. these voltages are generated internally. connect capacitors of c bx value between v bx+ and v bx? . the resistance of these traces direct ly affects the driving strength of seg electrodes and impacts the ima ge of the lcd module. minimize the trace resistance is critical in achieving high quality image. s b1+ s b1? s b0+ s b0? i wire to corresponding v b1/2x pin. merge ito traces between corresponding s bx and v bx in cog. v lcd-in v lcd-out pwr high voltage lcd power supply. connect these pins together. by-pass capacitor c l is optional. it can be connected between v lcd and v ss . when c l is used, keep the trace resistance under 300 ? . n ote ? recommended capacitor values: c b : 150~250x lcd load capacitance or 2.2f (2v), whichever is higher. c l : (optional) 5nf~50nf (16v) is appropriate for most applications. 1m/vr v dd2 / v dd3 v bias 330k
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 6 es specifications name type pins description h ost i nterface bm0 bm1 i bus mode: the interface bus mode is determined by bm[1:0] and d[7:6] by the following relationship: bm[1:0] d[7:6] mode 11 data 6800/8-bit 10 data 8080/8-bit 01 0x 6800/4-bit 00 0x 8080/4-bit 01 10 3-wire spi w/ 9-bit token (s9: conventional) 00 10 4-wire spi w/ 8-bit token (s8: conventional) 00 11 3/4-wire spi w/ 8-bit token (s8uc: ultra-compact) cs1 cs0 i 2 chip select. chip is selected when cs1=?h? and cs0 = ?l?. when the chip is not selected, d[7:0] will be high impedance. rst i when rst=?l?, all control registers are re -initialized by their default states. since uc1682 has built-in power-on reset and software reset command, rst pin is not required for proper chip operation. an rc filter has been included on-chip. there is no need for external rc noise filter. when rst is not used, connect the pin to v dd . cd i select control data or display data fo r read/write operation. in s9 modes, cd pin is not used. connect cd to v ss when not used. ?l?: control data ?h?: display data id i id pin is for production control. the connection will affect the content of d[7] when using get status command. connect to v dd for ?h? or v ss for ?l?. wr0 wr1 i wr[1:0] controls the read/write operat ion of the host interface. see host interface section for more detail. in parallel mode, wr[1:0] meaning depends on whether the interface is in the 6800 mode or the 8080 mode. in serial interface modes, these two pins are not used, connect them to v ss . d0~d7 i/o bi-directional bus for both seri al and parallel host interfaces. in serial modes, connect d[0] to sck, d[3] to sda, bm=1x (parallel) bm=0x (parallel) bm=01 (s9) bm=00 (s8/s8uc) d0 d0 d0/d4 sck sck d1 d1 d1/d5 ? ? d2 d2 d2/d6 ? ? d3 d3 d3/d7 sda sda d4 d4 ? ? ? d5 d5 ? ? ? d6 d6 ? 0 s8/s8uc d7 d7 0 1 1 connect unused pins to v ss .
uc1682 80x104rgb cstn controller-driver revision 0.6 7 name type pins description h igh v oltage lcd d river o utput seg1 ~ seg312 hv seg (column) driver outputs. support up to 104 x rgb pixels. leave unused drivers open-circuit. com1 ~ com80 hv com (row) driver outputs. support up to 80 rows. leave unused com drivers open-circuit. when designing lcm, always st art from com1. if the lcm has n pixel rows and n is less than 80, set cen to be n-1 , and leave com drivers [n+1 ~ 80] open-circuit. m isc . p ins v ddx o auxiliary v dd . these pins are connected to the main v dd bus on chip. they are provided to facilitate chip configurations in cog and cof applications. these pins should not be used to provide v dd power to the chip. it is not necessary to connect v ddx to main v dd externally. tst4 i/hv test control. this pin has on-chip pull-up/down resistor. leave it open during normal operation. tst4 is also used as one of the high voltage programming power supply for otp operation. for cog design wi th otp options, please wire out tst4 with an ito trace resistance of 200 ? or less. tst2 i/o test i/o pins. leave these pins open during normal use. tp[5:1] i test control. leave t hese pins open during normal use. note: several control registers will specify ?0 based index? for com and seg electrodes. in those situations, com x or seg x will correspond to index x -1, and the value ranges for those index registers will be 0~79 for com and 0~311 for seg.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 8 es specifications r ecommended cog l ayout users can use either otp control (through tst4 pin) or external circuit (through v bias pin) to fine tune v lcd. please refer to the following figures: f igure 1: example for tst4 cog layout when using otp control to fine tune v lcd f igure 2: example for v bias cog layout when using exter nal circuit to fine tune v lcd
uc1682 80x104rgb cstn controller-driver revision 0.6 9 r eference cog l ayout fpc bonding area com_pad<26> dummy2 com_pad<48> com_pad<46> com_pad<28> com_pad<24> com_pad<4> com_pad<2> dummy1 d0 d1 d2 d3 d4 d5 d6 vddx d7 com_pad<80> com_pad<78> com_pad<52> com_pad<50> seg_pad<312> seg_pad<311> vss2 vss2 vss2 vss vss vss vss vss vss prg1 prg2 prg3 tst1 tst2 tst3 tst4 tst4 bm1 vddx bm0 wr1 vddx wr0 cd cs0 vddx cs1 rst_ vref id vb1p vb1p vb1p vb1p vb1p vb0p_s vb0p vb0p vb0p vb0p vb0p vb0p vb0p vb0p vb0p vdd vdd vdd vdd vdd vdd vdd2 vdd2 vdd2 vdd2 vdd2 vdd3 vdd3 vdd3 vdd3 vss2 vss2 seg_pad<196> seg_pad<195> seg_pad<194> vlcdout vlcdout vlcdin vlcdin vb0n_s vb0n vb0n vb0n vb0n vb0n vb0n vb0n vb0n vb0n vb1n_s vb1n vb1n vb1n vb1n vb1n vb1n vb1n vb1n vb1n vb1p_s vb1p vb1p vb1p vb1p com_pad<49> com_pad<51> com_pad<77> com_pad<79> seg_pad<62> seg_pad<61> seg_pad<60> seg_pad<59> seg_pad<2> seg_pad<1> d7 d6 d5 d4 d3 d2 d1 d0 rst cs0 wr1 tst4 vss ~ vss2 vss ~ vss2 vss ~ vss2 vdd ~ vdd3 vdd ~ vdd3 vdd ~ vdd3 vdd ~ vdd3 vdd ~ vdd3 vb0+ ~ sb0+ cd wr0 vb0+ ~ sb0+ vb0+ ~ sb0+ vb1+ ~ sb1+ vb1+ ~ sb1+ vb1+ ~ sb1+ vb1- ~ sb1- vb1- ~ sb1- vb1- ~ sb1- vb1- ~ sb1- vb0- ~ sb0- vb0- ~ sb0- vb0- ~ sb0- vb0- ~ sb0- vlcd vlcd nc nc vss ~ vss2 vss ~ vss2 notes for v dd with cog: the v dd =1.8v-typ operation condition of uc1682 shou ld be met under all lcm formats. unless v dd , v dd2/3 ito trances can each be controlled to be 5 ? or lower, otherwise v dd -v dd2/3 separation can cause the actual on-chip v dd to drop below v dd =1.7v during high speed data write condition. therefore, for cog, v dd -v dd2/3 separation is not suitable fo r pure ito based cog designs.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 10 es specifications c ontrol r egisters uc1682 contains registers which control the chip operat ion. these registers can be modified by commands. the following table is a summary of the control regi sters, their meanings a nd their default values. commands supported by uc1682 will be described in the next two sections. first, a summary table, followed by a detailed instruction-by-instruction description. name: the symbolic reference of the register. note that, some symbol name refers to bits (flags) within another register. default: numbers shown in bold font are default values after power-up-reset and system-reset . name bits default description sl 7 0h scroll line. scroll the displayed image up by sl rows. the valid sl value is between 0 (for no scrolling) and (79? 2xfl ). setting sl outside of this range causes undefined effect on the displayed image. fl 4 0h fixed lines. the first flx2 lines of each frame are fixed and are not affected by scrolling (sl). when fl is non-zero, the screen is effectively separated into two regions: one scrollable, one non-scrollable. when partial display mode is activated, the display of these 2xfl lines is also controlled by lc[0]. cr 7 0h return column address. us eful for cursor implementation. ca 7 0h display data ram column address (counted in rgb triplet) (used in host to display data ram access) ra 7 0h display data ram row address (used in host to display data ram access) br 2 3h bias ratio. the ratio between v lcd and v bias . 00b: 5 01b: 7 10b: 8 11b: 9 tc 2 0h temperature compensation (per o c) 00b: -0.05% 01b: -0.10% 10b: -0.15% 11b: -0.20% pm 8 55h electronic potentiometer to fine tune v bias and v lcd pmo 6 20h pm offset. the effective pm value pmv = pm+pmo-32. make sure pmv formula does not overflow or underfl ow. (available only on otp version). om 2 ? operating modes (read only) 10b: sleep 11b: normal 01b: (not used) 00b: reset id 1 pin access the connected status of id pin. msk 3 0h r/g/b write data mask bits msk[2:0] = {mr, mg, mb} (default: 000b ) 0: write 1: block rs 1 reset in progress. host interface not ready pc 4 dh power control. pc[1:0]: 00b: lcd: 9nf 01b: lcd: 9~12nf 10b: lcd: 12~16nf 11b: lcd: 16~22nf pc[3:2]: 00b: external v lcd 11b: internal v lcd (standard)
uc1682 80x104rgb cstn controller-driver revision 0.6 11 name bits default description dc 5 18h display control: dc[0]: pxv: pixels inverse. bit-wise data inversion. (default 0: off ) dc[1]: apo: all pixels on (default 0: off ) dc[2]: display on/off (default 0: off ) dc[3]: gray-shade modulation mode. 0: 8-shade mode 1: 32-shade mode dc[4]: dither function control. 0: disable dither function 1: enable dither function ac 5 1h address control: ac[0]: wa: automatic column/row wrap around (default 1: on ) ac[1]: auto-increment order 0: column (ca) first 1: row (ra) first ac[2]: rid: ra (row addre ss) auto increment direction ( l:+1 h:-1) ac[3]: cum: cursor update mode, (default 0: off ) when cum=1, ca increment on write only, wrap around suspended ac[4] : window program enable 0 : disable 1 : enable wpc0 8 00h window program starting column address. value range: 0 ~103. wpp0 8 00h window program starting row address. value range: 0~79. wpc1 8 67h window program ending co lumn address. value range: 0~103. wpp1 8 4fh window program ending row address. value range: 0~79. otp operation for otp version ic, register wpc[1: 0] and wpp[1:0] are also used to control the otp operation (when otpc[3]=1). cen dst den 7 7 7 4fh 00h 4fh com scanning end (last com with full line cycle, 0 based index) display start (first com with active scan pulse, 0 based index) display end (last com with active scan pulse, 0 based index) please maintain the following relationship: cen = the actual number of pixel rows on the lcd - 1 cen den dst+ 9
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 12 es specifications name bits default description lc 10 090h lcd control: lc[0]: enable the first flx2 lines in partial display mode (default off ). lc[1]: mx, mirror x. seg/colum n sequence inversion (default: off ) lc[2]: my, mirror y. com/ro w sequence inversion (default: off ) lc[4:3]: line rate (klps: kilo-line-per-second) 00b: 10.0 klps 01b: 12.8 klps 10b: 16.0 klps 11b: 20.0 klps (frame-rate = line-rate / mux-rate) lc[5] : rgb filter order (as mapped to seg1, seg2, seg3) 0 : bgr-bgr 1 : rgb-rgb lc[7:6] : color and input mode for dither-enabled: 00b : 256 co lor mode. 3r-3g-2b (8-bit/rgb) 01b : 4k color mode. 4r-4g-4b (12-bit/rgb) 10b : 56k color mode . 5r-6g-5b (16-bit/rgb) 11b : 221k color mode. 6r-7g-5b (24-bit/rgb) for dither-disabled: 00b : 256 co lor mode. 3r-3g-2b (8-bit/rgb) 01b : 4k color mode. 4r-5g-3b (12-bit/rgb) 10b : 4k color mode. 5r-6g-5b (16-bit/rgb) 11b : 4k color mode. 6r-7g-5b (24-bit/rgb) for data over 4r-5g-3b, each redundant lsb of each color will be truncated. (example: for r4r3r2r1r0 - g5g4g3g2g1g0 - b4b3b2b1b0 , r0, g0, b1, and b0 will be truncated.) lc[9:8] : partial display control 0xb: disable mux-rate = cen+1 (dst, den not used) 10b: enabled mux-rate = cen+1 11b: enabled mux-rate = den-dst+1+lc[0]x2xfl apc0 apc1 5 8 0dh 36h advanced program control. for ultrachip only. please do not use. od 1 ? otp option flag 0: no otp 1: with otp os 1 ? otp programming in-progress ws 1 ? otp command succeeded otpc 6 10h otp programming control: otp0[2:0] : otp command 000 : sleep 001 : read 010 : erase 011 : program 1xx : for ultrachip use only otp[3] : otp enable ( auto clear after otp command action done ) otp[4] : use/ignore otp value. 0: ignore 1: normal otp[5] : otp command enable otpm 8 00h otp write mask
uc1682 80x104rgb cstn controller-driver revision 0.6 13 c ommand t able the following is a list of host commands supported by uc1682 c/d: 0: control, 1: data w/r: 0: write cycle, 1: read cycle # useful data bits ? don?t care command c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 action default 1 write data byte 1 0 # ####### write 1 byte n/a 2 read data byte 1 1 # ####### r ead 1 byte n/a 3 get status 0 1 id mx my wa de ws od os get status n/a set column address lsb 0 0 0000#### set ca [3:0] 0 4 set column address msb 0 0 0 0 0 1 - # # # set ca[6:4] 0 5 set temp. compensation 0 0 0 01001## set tc [1:0] 0 6 set panel loading 0 0 0 01010## set pc [1:0] 1 7 set pump control 0 0 0 01011## set pc [3:2] 11b 0 0 0011000r 8 set adv. program control (double byte command) 0 0 ######## set apc[r][7:0], r = 0, or 1 n/a set scroll line lsb 0 0 0100#### set s l[3:0] 0 9 set scroll line msb 0 0 0 1 0 1 - # # # set sl[6:4] 0 set row address lsb 0 0 0110#### set ra [3:0] 0 10 set row address msb 0 0 0 1 1 1 - # # # set ra[6:4] 0 11 set v bias potentiometer (double-byte command) 0 0 0 0 1 # 0 # 0 # 0 # 0 # 0 # 0 # 1 # set pm[7:0] 55h 12 set partial display control 0 0 1 00001## set lc [9:8] 0: disable 13 set ram address control 0 0 1 0001### set ac [2:0] 001b 14 set fixed lines 0 0 1001#### set f l[3:0] 0 15 set line rate 0 0 1 01000## set lc [4:3] 10b 16 set all-pixel-on 0 0 1010010# set dc [1] 0 17 set inverse display 0 0 1010011# set dc [0] 0 18 set display enable 0 0 1 0101### set dc [4:2] 110b 19 set color mask 0 0 10110### set msk [2:0] 0 20 set lcd mapping control 0 0 1 1000### set lc [2:0] 0 21 set color pattern 0 0 1 101000# set lc [5] 0 (bgr) 22 set color mode 0 0 1 10101## set lc [7:6] 10b (56k) 23 system reset 0 0 11100010 system reset n/a 24 nop 0 0 11100011 no operation n/a 0 0 111001 tt 25 set test control (double byte command) 0 0 ######## for testing only. do not use. n/a 26 set lcd bias ratio 0 0 111010## set br [1:0] 11b: 9 27 reset cursor update mode 0 0 1 1101110ac [3]=0, ca=cr ac[3]=0 28 set cursor update mode 0 0 1 1101111ac [3]=1, cr=ca ac[3]=1 29 set com end 0 0 0 0 1 - 1 # 1 # 1 # 0 # 0 # 0 # 1 # set cen[6:0] 79 30 set partial display start 0 0 0 0 1 - 1 # 1 # 1 # 0 # 0 # 1 # 0 # set dst[6:0] 0 31 set partial display end 0 0 0 0 1 - 1 # 1 # 1 # 0 # 0 # 1 # 1 # set den[6:0] 79 32 set window program starting column address 0 0 0 0 1 # 1 # 1 # 1 # 0 # 1 # 0 # 0 # set wpc0[7:0] 0 33 set window programming starting row address 0 0 0 0 1 # 1 # 1 # 1 # 0 # 1 # 0 # 1 # set wpp0[7:0] 0 34 set window programming ending column address 0 0 0 0 1 # 1 # 1 # 1 # 0 # 1 # 1 # 0 # set wpc1[7:0] 103 35 set window programming ending row address 0 0 0 0 1 # 1 # 1 # 1 # 0 # 1 # 1 # 1 # set wpp1[7:0] 79 36 enable window program 0 0 1 111100# set ac [4] 0: disable * other than commands listed above, all other bit patterns may result in undefined behavior.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 14 es specifications otp command c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 action default 37 set otp operation control 0 0 0 0 1 - 0 - 1 # 1 # 1 # 0 # 0 # 0 # set otp0[5:0] 0 38 set otp write mask 0 0 0 0 1 # 0 # 1 # 1 # 1 # 0 # 0 # 1 # set otp1[7:0] 0 39 set v otp1 potentiometer 0 0 0 0 1 # 1 # 1 # 1 # 0 # 1 # 0 # 0 # 40 set v otp2 potentiometer 0 0 0 0 1 # 1 # 1 # 1 # 0 # 1 # 0 # 1 # 41 set otp write timer 0 0 0 0 1 # 1 # 1 # 1 # 0 # 1 # 1 # 0 # 42 set otp read timer 0 0 0 0 1 # 1 # 1 # 1 # 0 # 1 # 1 # 1 # shared with window programming commands n/a ? other than commands listed above, all other bit patterns may result in undefined behavior. ? the otp commands listed above should only be used with otp version of uc1682. ? command 39~42 are shared with command 32~35, and they have exactly the same code. the interpretation of these four commands depends on re gister otpc[3]. when otpc[3]=0, they are interpreted as window programming commands. when otpc[3]=1, they are otp control commands. ? otpm and pm are actually the same register. the usage of this register is de termined by otpc[3] in similar ways as command 39~42. ? after otp-erase or otp-program operat ion (set otpc[3]=1) , always a) remove tst4 power source; b) do a full vdd on-off cycle; before resuming normal operation.
uc1682 80x104rgb cstn controller-driver revision 0.6 15 c ommand d escription (1) w rite d ata t o d isplay m emory action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 write data 1 0 8bits dat a write to sram uc1682 will convert input ram da ta to 12-bits of rgb data. please refer to command (22) set color mode for detail data write sequence. the format of 12 bits rgb data is as following: d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r g b (2) r ead d ata f rom d isplay m emory action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 read data 1 1 8bits data from sram each rgb triplet is stored as 12-bit in the display ram. each 12 bits rgb data takes 2 ram read cycles. the data read will start with the high byte d[11:4] and then low byte {d[3:0],4?b0000}. the read out rgb data is after-dither for 56k color and 221k color mode and after-extension for 256 color mode. r3 r2 r1 r0 g4 g3 g2 g1 g0 b2 b1 b0 0 0 0 0 1st read 2nd read write/read data byte (command 1/2) operation uses internal row address register (ra) and column address register (ca). ra and ca can be programmed by issuing set row address and set column address commands. if wrap-around (wa, ac[0 ]) is off (0), ca will stop in crementing after reaching the ca boundary, and system programmers need to set the values of ra and ca explicitly. if wa is on (1), when ca reaches end of column address, ca will be reset to 0 and ra will be increased or decreased, depending on the setting of row increment direction (rid, ac[2 ]). when ra reaches the boundary of ram (i.e. ra = 0 or 79), ra will be wrapped around to the other end of ram and continue. (3) g et s tatus action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 get status 0 1 id mx my wa de ws od os status flag definitions: id : provide access to id pin connection status. mx : status of register lc[1], mirror x. my : status of register lc[2], mirror y. wa: status of register ac[0]. automatic column/row wrap around. de : display enable flag. de=1 when display is enabled ws : otp command succeeded od : otp option (yes/no) os : otp action status (4) s et c olumn a ddress action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set column address lsb ca[3:0] 0 0 0000 ca3 ca2 ca1 ca0 set column address msb ca[6:4] 0 0 0001 - ca6 ca5 ca4 set sram column address for read/write access. ca is counted in rgb triplets, not individual seg electrode. ca value range: 0~103
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 16 es specifications (5) s et t emperature c ompensation action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set temperature comp. tc[1:0] 0 0 001001tc1 tc0 set v bias temperature compensation coefficient (%-per-degree-c) temperature compensati on curve definition: 00b = -0.05%/ o c 01b= -0.10%/ o c 10b= -0.15%/ o c 11b= -0.20%/ o c (6) s et p anel l oading action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set panel loading pc[1:0] 0 0 001010 pc1 pc0 set pc[1:0] according to the capacitance loading of lcd panel. panel loading definition: 00b 9nf 01b = 9~12nf 10b= 12~16nf 11b= 16~22nf (7) s et p ump c ontrol action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set pump control pc[3:2] 0 0 001011 pc3 pc2 set pc[3:2] to program the build-in charge pump stages. pump control definition: 00b=external vlcd 11b = internal vlcd (standard) (8) s et a dvanced p rogram c ontrol action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 0011000 r set apc[1:0] (double byte command) 0 0 apc register parameter for ultrachip only. please do not use. (9) s et s croll l ine action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set scroll line lsb sl[3:0] 0 0 0100 sl3 sl2 sl1 sl0 set scroll line msb sl[6:4] 0 0 0101 - sl6 sl5 sl4 set the scroll line number. scroll line setting will scroll the displayed image up by sl rows. the valid value for sl is between 0 (no scrolling) and (79-2xfl). fl is the register value programmed by set fixed lines command. sl=0 sl=n image row 0 ???. image row n ???. image row 79 image row n ???. image row 79 image row 0 ??? image row n-1
uc1682 80x104rgb cstn controller-driver revision 0.6 17 (10) s et r ow a ddress action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set row address lsb ra [3:0] 0 0 0110 ra3 ra2 ra1 ra0 set row address msb ra [6:4] 0 0 0111 - ra6 ra5 ra4 set sram row address for read/write access. possible value = 0~79 (11) s et v bias p otentiometer action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1000000 1 set v bias potentiometer. pm [7:0] (double byte command) 0 0 pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 program v bias potentiometer (pm[7:0]). see section lcd v oltage s etting for more detail. effective range: 0 ~ 255 (12) s et p artial d isplay c ontrol action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set partial display enable lc [9:8] 0 0 100001 lc9 lc8 this command is used to enable partial display function. lc[9:8] : 0x b: disable partial display, mux-rate = cen+1 (dst, den not used.) 10b: enable partial display, mux-rate = cen+1 11b: enable partial display, mux-rate = den-dst+1+lc[0]x2xfl (13) s et ram a ddress c ontrol action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set ac [2:0] 0 0 10001 ac2 ac1 ac0 program registers ac[2:0] fo r ram address control. ac[0]: wa, automatic column/row wrap around. 0: ca or ra (depends on ac[1]= 0 or 1) will stop incrementing after reaching boundary 1 : ca or ra (depends on ac[1]= 0 or 1) will rest art, and ra or ca will increment by one step. ac[1]: auto-increment order 0 : column (ca) increment (+1) first until ca reac hes ca boundary, then ra will increment by (+/-1). 1 : row (ra) increment (+/-1) first until ra r each ra boundary, then ca will increment by (+1). ac[2]: rid, row address (r a) auto increment direction ( 0 /1 = +/- 1 ) when wa=1 and ca reaches ca boundary, rid controls whether row address will be adjusted by +1 or -1. ac[2:0] controls the auto-increment behavior of ca and ra. when window program is enabled (ac[4]=on), see command description (32) ~ (36) for more details. if wpc[1:0] and wpp[1:0] values are the default values, the behavior of ca, ra auto-increment will be the same, no matter what the setting of ac[4] is.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 18 es specifications (14) s et f ixed l ines action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set fixed lines fl [3:0] 0 0 1001 fl3 fl2 fl1 fl0 the fixed line function is used to implement the partial scroll function by dividing the screen into scroll and fixed area. set fixed lines command will define the fixed area, which will not be affected by the sl scroll function. the fixed area covers the top 2xfl rows for mirror y (my) is 0 and bottom 2xfl rows for my=1. one example of the visual effect on lcd is illustrated in the figure below. my = 0 my = 1 when partial display mode is activated, the display of these 2xfl lines is also controlled by lc[0]. ]. before turning on lc[0], please make sure my=0 dst >= flx2 my=1 dst >= 0 den <= cen. den <= cen-flx2 (15) s et l ine r ate action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set line rate lc [4:3] 0 0 101000 lc4 lc3 program lc [4:3] for line rate setting (frame-rate = line-rate / mux-rate). the line rate is automatically scaled down by 1/2 and 1/3 at mux-rate = 38 and 24. the following are line rates at mux rate = 39 ~ 80. 00b: 10.0 klps 01b: 12.8 klps 10b: 16.0 klps 11b: 20.0 klps (klps: kilo-line-per-second) (16) s et a ll p ixel on action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set all pixel on dc [1] 0 0 1010010 dc1 set dc[1] to force all seg drivers to output on signals. this function has no effect on the existing data stored in display ram. (17) s et i nverse d isplay action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set inverse display dc [0] 0 0 1010011 dc0 set dc[0] to force all seg drivers to output the inverse of the data (bit-wise) stored in display ram. this function has no effect on the existing data stored in display ram. fixed area 1 ( 2xfl ) scroll area 80 scroll area 1 fixed area (2xfl) 80
uc1682 80x104rgb cstn controller-driver revision 0.6 19 (18) s et d isplay e nable action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set display enable dc [4:2] 0 0 10101 dc4 dc3 dc2 this command is for programming register dc[4:2]. when dc[2] is set to 0 , the ic will put itself into sleep mode. all drivers, voltage generation circuit and timing circuit will be halted to conserve power. when dc[2] is set to 1, uc1682 will first exit from sleep mode, restore the power and then turn on com drivers and seg dr ivers. there is no other explicit user action or timing sequence required to enter or exit the sleep mode. dc[3] controls the gray shade modulation modes . uc1682 has two gray shade modulation modes: an 8- sahde mode and a 32-shade mode. the modulation curves are shown below. horizontal axes are the gray shade data. the vertical axes are the on-off ratio. 9/9 is 100% on for 8-shade mode, 51/51 is 100% on for 32-shade mode. 0 3 6 9 12 34 56 7 8 0 5 10 15 20 25 30 35 40 45 50 1 4 7 1013161922252831 dc[4] enables dither function. refer to (22) set color mode for more information. 0b: disable 1b: enable
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 20 es specifications (19) s et c olor m ask action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set color mask msk [2:0] 0 0 10110 msk[2:0] this command is used for program msk[2:0] which will control whether the input rgb data will be blocked from updating rgb data in the ram. (1: block, 0: normal. msk[2:0] = {msk_r, msk_g, msk_b}) example: let color mode = 256 colo r, msk[2:0] = 100b (msk_r = 1, msk_ g = 0, msk_b = 0). there is one pixel to be updated, and the original data for the pixel is 11100110b ( rrr - ggg - bb ). suppose the new input rgb data is 00000000b, since r is masked, the data for the pixel would be updated as 11100000b. (20) s et lcd m apping c ontrol action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set lcd mapping control lc [2:0] 0 0 11000 my mx lc0 this command is used for program lc[2:0] for com (row) mirror (my), seg (column) mirror (mx). lc[2] controls mirror y (my): my is implement ed by reversing the mapping order between ram and com electrodes. the data stored in ra m is not affected by my command. my will have immediate effect on the display image. lc[1] controls mirror x (mx): mx is implemented by selecting the ca or 103-ca as write/read (from host interface) display ram column address so this functi on will only take effect after rewriting the ram data. lc[0] controls whether the soft icon section (0~ 2x fl) is display or not duri ng partial display mode. (21) s et c olor p attern action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set color pattern lc [5] 0 0 1101000 lc5 uc1682 supports on-chip swapping of r b data mapping to the seg drivers. lc[5] seg1 seg2 seg3 seg4 seg5 seg6 ? seg304 seg311 seg312 0 b g r b g r ? b g r 1 r g b r g b ? r g b the definition of r/g/b input data is determined by lc[7:6], as described in set color mode below.
uc1682 80x104rgb cstn controller-driver revision 0.6 21 (22) s et c olor m ode action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set color mode lc [7:6] 0 0 110101 lc7 lc6 program color mode and rgb input patte rn. color mode (lc[7:6]) definition: dither options: dc[4]=1b enables dither function. refer to (18) set display enable for more information. lc[7:6] = 00b ( rrr - ggg - bb , 256 color ) one byte of input data is extended and stored to 12 ram bits. data write sequence d[7:0] 1 st byte write data r2 r1 r0 g2 g1 g0 b1 b0 lc[7:6] = 01b ( rrrr - gggg - bbbb , 4k color ) 1-bit extension for g, 1-bit dither for b. 12 bits of input data is stored to 12 ram bits. 3 bytes of input data will be merged into 2 sets of rgb data. data write sequence d[7:0] 1 st byte write data r3 r2 r1 r0 g3 g2 g1 g0 2 nd byte write data b3 b2 b1 b0 r3 r2 r1 r0 3 rd byte write data g3 g2 g1 g0 b3 b2 b1 b0 lc[7:6] = 10b ( rrrrr - gggggg - bbbbb , 56k color ) 1-bit dither for r/g, 2-bit dither for b. 16 bits input data dith ered to 12 ram bits. data write sequence d[7:0] 1 st byte write data r4 r3 r2 r1 r0 g5 g4 g3 2 nd byte write data g2 g1 g0 b4 b3 b2 b1 b0 lc[7:6] = 11b ( rrrrrr - ggggggg - bbbbb , 221k color ) 2-bit dither per color. 18 out of 24 bits input data is dithered to 12 ram bits. data write sequence d[7:0] 1 st byte write data r5 r4 r3 r2 r1 r0 -- -- 2 nd byte write data g6 g5 g4 g3 g2 g1 g0 -- 3 rd byte write data b4 b3 b2 b1 b0 -- -- -- data read sequence for lc[7:6] = 0. data read sequence d[7:0] 1 st byte read data r2 r1 r0 r m g2 g1 g0 g m2 2 nd byte read data g m1 b2 b1 b0 0 0 0 0 r/g/b: the input red/green/blue data. r/g mn : the red/green bits mapped from rgb input data. for lc[7:6] = 1, 2, 3. data read sequence d[7:0] 1 st byte read data r d3 r d2 r d1 r d0 g d4 g d3 g d2 g d1 2 nd byte read data g d0 b d2 b d1 b d0 0 0 0 0 r/g/b dn : the n-th bit of after-di ther red/green/blue input data note : for system designers who want to use their own di thering algorithm, please set lc[7:6] = 10b (56k color mode) and use the following input patte rn to bypass on-chip dithering algorithm: r3-r2-r1-r0 -1- g4-g3-g2-g1-g0 -1- b2-b1-b0 -1-0
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 22 es specifications no-dither options: dc[4]=0b disables dither function. refer to (18) set display enable for more information. lc[7:6] = 00b ( rrr - ggg - bb , 256 color ) one byte of input data is extended and stored to 12 ram bits. data write sequence d[7:0] 1 st byte write data r2 r1 r0 g2 g1 g0 b1 b0 lc[7:6] = 01b ( rrrr - ggggg - bbb , 4k color ) 12 bits of input data is stored to 12 ram bits. 3 bytes of input data will be merged into 2 sets of rgb data. data write sequence d[7:0] 1 st byte write data r3 r2 r1 r0 g4 g3 g2 g1 2 nd byte write data g0 b2 b1 b0 r3 r2 r1 r0 3 rd byte write data g4 g3 g2 g1 g0 b2 b1 b0 lc[7:6] = 10b ( rrrrr - gggggg - bbbbb , 56k color ) 1-bit truncation for r/g, 2-bit for b. 16 bits input data truncated to 12 ram bits. data write sequence d[7:0] 1 st byte write data r4 r3 r2 r1 r0 g5 g4 g3 2 nd byte write data g2 g1 g0 b4 b3 b2 b1 b0 lc[7:6] = 11b ( rrrrrr - ggggggg - bbbbb , 221k color ) 2-bit truncation for per color. 18 out of 24 bits input data is truncated to 12 ram bits. data write sequence d[7:0] 1 st byte write data r5 r4 r3 r2 r1 r0 -- -- 2 nd byte write data g6 g5 g4 g 3g2g1g0 -- 3 rd byte write data r4 r3 r2 r1 r0 -- -- -- data read sequence for lc[7:6] = 0. data read sequence d[7:0] 1 st byte read data r2 r1 r0 r m g2 g1 g0 g m2 2 nd byte read data g m1 b2 b1 b0 0 0 0 0 r/g/b: the input red/green/blue data. r/g mn : the red/green bits mapped from rgb input data. for lc[7:6] = 1, 2, 3. data read sequence d[7:0] 1 st byte read data r t3 r t2 r t1 r t0 g t4 g t3 g t2 g t1 2 nd byte read data g t0 b t2 b t1 b t0 0 0 0 0 r/g/b tn : the n-th bit of after-trun cated red/green/blue input data (23) s ystem r eset action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 system reset 0 0 1110001 0 this command will activate the system reset. control regi ster values will be reset to their default values. data stored in ram will not be affected.
uc1682 80x104rgb cstn controller-driver revision 0.6 23 (24) nop action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 no operation 0 0 1110001 1 this command is used for ?no operation?. (25) s et t est c ontrol action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 111001 tt set tt (double byte command) 0 0 testing parameter this command is used for ultrachip production testing. please do not use. (26) s et lcd b ias r atio action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set bias ratio br [1:0] 0 0 111010 br1 br0 bias ratio definition: 00b= 5 01b=7 10b=8 11b =9 (27) r eset c ursor u pdate m ode action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 reset cursor update mode ac[3]=0 ca=cr 00 1110111 0 this command is used to reset cursor update mode function. (28) s et c ursor u pdate m ode action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set ac[3]=1 cr=ca 0 0 1110111 1 this command is used for set cursor update mode function. when cursor update mode is set, uc1682 will update register cr with the value of register ca. the column address ca will increment with write ram data operation but the address wraps around will be suspended no matter what wa setting is. however, the column address will not increment in read ram data operation. the set cursor update mode can be used to implement ?w rite after read ram? function. the column address (ca) will be restored to the value, which is before the set cursor update mode command, when resetting cursor update mode. the purpose of this pair of commands and their features is to support ?write afte r read? function for cursor implementation. (29) s et com e nd action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111000 1 set cen (double byte command) 00 cen register parameter this command programs the ending com electrode. cen defines the number of used com electrodes, and it should correspond to the number of pixel-rows in the lcd.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 24 es specifications (30) s et p artial d isplay s tart action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111001 0 set dst (double byte command) 00 dst register parameter this command programs the starting com electrode, which has been assigned a full scanning period and will output an active com scanning pulse. (31) s et p artial d isplay e nd action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111001 1 set den (double byte command) den register parameter this command programs the ending com electrode, which has been assigned a full scanning period and will output an active com scanning pulse. cen, dst, and den are 0-based index of com electrod es. they control only the com electrode activity, and do not affect the mapping of display ram to ea ch com electrodes. the image displayed by each pixel row is therefore not affected by the setting of these three registers. when lc[9]=1, two partial display modes are possible with uc1682: lc[8]=1: on-off only, ultra-low-power mode (if mux-rate 32, set br=5). lc[8]=0: full gray shade low power mode (br and pm stays the same) when lc[9:8]=11b, the mux-rate is narrowed down to just the range between dst and den. when mux- rate is under 32, set br=5, pc[3:2]=01b, and adjust pm to reduce vlcd and achieve the lowest power consumption. when lc[9:8]=10b, the mux-rate is still cen+1. this is achieved by suppressing only the scanning pulses, but not the scanning time slots, for com electrodes that is outside of dst~den. under this mode, the gray-scale quality of the display is pr eserved, while the power can be reduced significantly. in either case, dst/den defines a small subsection of the display which will remain ac tive while shutting down all the rest of the display to conserve energy. 0 dst den pulse disable: cen pulse enable: not scanned: 79 (32) s et w indow p rogram s tarting c olumn a ddress action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111010 0 set wpc0 (double byte command) wpc0[7:0] register parameter this command is to program the starting column address of ram program window.
uc1682 80x104rgb cstn controller-driver revision 0.6 25 (33) s et w indow p rogram s tarting r ow a ddress action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111010 1 set wpp0 (double byte command) wpp0 register parameter this command is to program the starting row address of ram program window. (34) s et w indow p rogram e nding c olumn a ddress action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111011 0 set wpc1 (double byte command) wpc1[7:0] register parameter this command is to program the ending column address of ram program window. (35) s et w indow p rogram e nding r ow a ddress action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111011 1 set wpp1 (double byte command) wpp1 register parameter this command is to program the ending row address of ram program window. (36) s et w indow p rogram e nable action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 set window program enable ac[4] 0 0 1111100 ac4 this command is to enable the window program functi on. window program enable should always be reset when changing the window program boundary and then set right before starting the new boundary program. window program function can be used to refresh the ra m data in a specified window of sram address. when window programming is enabl ed, the ca and ra increment and wrap around will be automatically adjusted, and therefore allow effect ive data update within the window. the direction of window program will depend on the wa (ac[0]), rid (ac[2]), auto-increment order (ac[1]) and mx (lc[1]) register setting. wa decides whet her the program ram address advances to next row/column after reaching the specified window colu mn / row boundary. rid controls the ram address incrementing from wpp0 toward wpp1 (rid=0) or re verse the direction (rid=1 ). auto-increment order directs the ram address increment vertically (ac[1]=1 ) or horizontally (ac[1]=0). mx results the ram column address incrementing from 103-wpc0 to 1 03-wpc1 (mx=1) or wp c0 to wpc1 (mx=0).
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 26 es specifications auto-increment order = 0 mx=0 rid = 0 (wpp0,wpc0) (wpp1,wpc1) auto-increment order = 1 mx=0 rid = 0 (wpp0,wpc0) (wpp1,wpc1) auto-increment order = 0 mx=0 rid = 1 (wpp0,wpc0) (wpp1,wpc1) auto-increment order = 0 mx=1 rid = 0 (wpp0,103-wpc0) (wpp1,103-wpc1)
uc1682 80x104rgb cstn controller-driver revision 0.6 27 auto-increment order = 1 mx=0 rid = 1 (wpp0,wpc0) (wpp1,wpc1) auto-increment order = 1 mx=1 rid = 0 (wpp0,103-wpc0) (wpp1,103-wpc1) auto-increment order = 0 mx=1 rid = 1 (wpp0,103-wpc0) (wpp1,103-wpc1) auto-increment order = 1 mx=1 rid = 1 (wpp0,103-wpc0) (wpp1,103-wpc1)
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 28 es specifications (37) s et otp c ontrol action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1011100 0 set otpc (double byte command) otp0 register parameter this command is for otp operation control: otpc[2:0] : otp command 000 : sleep 001 : otp read 010 : otp erase 011 : otp program 1xx : for ultrachip use only. otpc[3] : otp enable (automatically clear ed each time after otp command is done) otpc[4] : otp value valid ( ignore otp value when l ) otpc[5] : otp operation mode ? set [5] before otp external v connection (38) s et otp w rite m ask action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1011100 1 set otpm (double byte command) otp1 register parameter this command is enable write to each of the 8 individual otp bits (39) s et v otp1 p otentiometer action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111010 0 set otp2 (double byte command) otp2 register parameter this command is for fine tuning v opt1 setting (use with br=00) (40) s et v otp2 p otentiometer action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111010 1 set otp3 (double byte command) otp3 register parameter this command is for fine tuning v otp2 pm setting (use with br=10) (41) s et otp w rite t imer action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111011 0 set otp4 (double byte command) otp4 register parameter (42) s et otp r ead t imer action c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 00 1111011 1 set otp5 (double byte command) otp5 register parameter
uc1682 80x104rgb cstn controller-driver revision 0.6 29 lcd v oltage s etting m ultiplex r ates multiplex rate is completely software programmable in uc1682 via registers cen, dst, den, and partial display control lc[9:8]. combined with low power partial display mode and a low bias ratio of 5, uc1682 can support wide variety of display control options. for example, when a system goes into stand-by mode, a large portion of lcd screen can be turned off to conserve power. b ias r atio s election bias ratio ( br ) is defined as the ratio between v lcd and v bias , i.e. br = v lcd /v bias , where v bias = v b1+ ? v b1? = v b0+ ? v b0? . the theoretical optimum bias ratio can be estimated by 1 + mux . br of value 15~20% lower/higher than the optimum value calculated above will not cause significant visible change in image quality. due to the nature of stn operation, an lcd designed for good gray-shade performance at high mux rate (e.g. mr=80), can generally perform very well as a black and white display, at lower mux rate. however, it is also true that such technique generally can not maintain lcd?s quality of gray shade performance, since the contrast of the lcd will increase as mux rate decreases, and the shades near the two ends of the spectrum will start to lose visibility. uc1682 supports four br as listed below. br can be selected by software program. br 0 1 2 3 bias ratio 5 7 8 9 table 1: bias ratios t emperature c ompensation four (4) different temperature compensation coefficients can be selected via software. the four coefficients are given below: tc 0 1 2 3 % per o c -0.05 -0.10 -0.15 -0.20 table 2: temperature compensation v lcd g eneration v lcd may be supplied either by internal charge pump or by external power supply. the source of v lcd is controlled by pc[3:2]. for good product reliability, it is recommended to keep v lcd under 12v over the entire operating range. when v lcd is generated internally, the voltage level of v lcd is determined by three control registers: br (bias ratio), pm (potentiometer), and tc (temperature compensation), with the following relationship: %) ) 25 ( 1 ( ) ( 0 t pm v lcd c t pm c c v ? + + = where c v0 and c pm are two constants, whose value depends on the setting of br register, as illustrated in the tabl e on the next page, pm is the numerical value of pm register, t is the ambient temperature in o c, and c t is the temperature compensation coefficient as selected by tc register. v lcd f ine t uning gray shade and color stn lcd is sensitive to even a 1% mismatch between ic driving voltage and the v op of lcd. however, it is difficult for lcd makers to guarantee such high precision matching of parts from di fferent venders. it is therefore necessary to adjust v lcd to match the actual v op of the lcd. for the best results, software or otp based v lcd adjustment is the recommended method for v lcd fine tuning. for applications where mechanical manual fine tuning of v lcd becomes necessary, then v bias pin may be used with an external trim pot to fine tune the v lcd . l oad d riving s trength the power supply circuit of uc1682 is designed to handle lcd panels with load capacitance up to ~20nf when v dd2 = 2.5v. for larger lcd panels use higher v dd and cof packaging. 20nf is also the recommended limit for lcd panel size for cog applications.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 30 es specifications v lcd q uick r eference 4 5 6 7 8 9 10 11 12 13 14 0 32 64 96 128 160 192 224 256 pm vlcd vlcd-pm relationship for different br setting at 25 o c. br c v0 (v) c pm (mv) pm v lcd (v) 0 4.47 5 4.474 12.50 255 7.66 0 6.21 7 6.206 17.50 255 10.67 0 7.07 8 7.070 20.00 255 12.17 0 7.93 9 7.931 22.50 255 13.67 note: 1. for good product reliability, keep vlcd under 10.3v at room temperat ure, and keep vlcd under 10.5v under all temperature and operating conditions. 2. the integer values of br above are for re ference only and probably have slight shift.
uc1682 80x104rgb cstn controller-driver revision 0.6 31 h i - v g enerator and bias reference circuit cl vdd2 sb0+ sb1+ vdd rl cb1+ (optional) sb1- cb1 cb0 sb0- (optional) 30pf for applications with vlcd over 11v vlcdin vb0- vdd vlcdout uc1682 vb0+ vss vb1- vdd2/vdd3 vdd3 vb1+ vss2 f igure 3: reference circuit using inte rnal hi-v generator circuit vdd2 vss sb0- vb0- r1 vdd (optional) vdd2/vdd3 vb1+ vb1- cb0 cbias vbias vlcdin (optional) 10~30pf for applications with vlcd over 11v sb1- uc1682 cb1+ cl vlcdout cb1 sb0+ vdd3 rl vss2 vdd vb0+ vr sb1+ f igure 4: reference circuit using external bias source note sample component values: (the illustrated circuit and component values are for reference only. please optimize for specific requirem ents of each application.) c b : 150 ~ 250x lcd load capacitance or 2.2f (2v), whichever is higher. c l : 5nf ~ 50nf (16v) is appropria te for most applications. r l : 3 ~ 10m ? , rc time constant of cl x rl should be roughly 0.2~1sec v r : 1m ? r 1 : 330k ? c bias : 10nf ~ 0.1uf is the recommended default value (not required for otp version).
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 32 es specifications lcd d isplay c ontrols c lock & t iming g enerator uc1682 contains a built-in system clock. all required components for the clock oscillator are built-in. no external parts are required. four different line rates are provided for system design flexibility. the line rate is controlled by register lc[4:3]. when mux-rate is above 38, frame rate is calculated as: frame rate = line-rate / mux-rate. when mux-rate is lowered to 38 (and 24), line rate will be scaled down by 2 (and 3) times automatically reduce power consumption. flicker-free frame rate is dependent on lc material and gray-shade modulation scheme. frame rate 175hz is recommended for 32-shade mode. choose lower frame rate for lower power, and choose higher frame rate to improve lcd contrast and minimize flicker. when switching from 32-shade modulation to 8- shade modulation, line rate will be scaled down automatically by ~30%. under most situations, flicker behavior is similar between these two different modulation schemes. when switching from 32-shade modulation to 8- shade modulation, line rate will be scaled down automatically by ~35%. under most situations, flicker behavior is similar between these two different modulation schemes. however, it is always recommended to test each mode to make sure flicker behavior is acceptable d river m odes com and seg drivers can be in either idle mode or active mode, controlled by display enable flag (dc[2]). when seg drivers are in idle mode, they will be connected together to ensure zero dc condition on the lcd. d river a rrangements the naming conventions are: com(x), where x=1~80, refers to the com driver for the x-th row of pixels on the lcd panel. the mapping of com(x) to lcd pixel rows is fixed and it is not affected by sl, cst, cen, dst, den, mx or my settings. d isplay c ontrols there are three groups of display control flags in the control register dc: driver enable (de), all- pixel-on (apo) and inverse (pxv). de has the overriding effect over pxv and apo. d river e nable (de) driver enable is controlled by the value of dc[2] via set display enable command. when dc[2] is set to off (logic ?0?), both com and seg drivers will become idle and uc1682 will put itself into sleep mode to conserve power. when dc[2] is set to on, the de flag will become ?1?, and uc1682 will first exit from sleep mode, restore the power (v lcd , v d etc.) and then turn on com and seg drivers. a ll p ixels o n (apo) when set, this flag will force all seg drivers to output on signals, disregarding the data stored in the display buffer. this flag has no effect when display enable is off and it has no effect on data stored in ram. i nverse (pxv) when this flag is set to on, seg drivers will output the inverse of the value it received from the display buffer ram (bit-wise inversion). this flag has no impact on data stored in ram. p artial s croll control register fl specifies a region of rows which are not affected by the sl register. since sl register can be used to implement scroll function. the fl register can be used to implement fixed region when the other part of the display is scrolled by sl. p artial d isplay uc1682 provides flexible control of mux rate and active display area. please refer to command set com end, set partial display start , and set partial display end for more detail. g ray - shade m odulation m ode uc1682 has two gray-shade modulation modes: 32-shade and 8-shade. the 8-shade mode will consume ~30% less power than the 32-shade mode, and can be used for situations where power consumption is more critical than color fidelity. changing gray-shade modulation mode does not affect the content of sram display buffer, and the image data will remain the same after switching back and forth between 8-shade mode and 32-shade mode.
uc1682 80x104rgb cstn controller-driver revision 0.6 33 i nput c olor f ormats uc1682 supports the followi ng four different input color formats. 256c (8-bit/rgb) : this is the most compact color mode, and is intended to minimize the bus cycle required to refresh the display buffer. on- chip extension circuit will automatically expand the input rgb data into on-chip ram buffer format. 4kc (12-bit/rgb) : in this color mode, g will be extended while b will be dithered, and the input data will be converted into 4r-5g-3b format before they are stored to display ram. 56kc (16-bit/rgb) : on-chip dither engine will convert the input data into internal 12-bit-per- rgb pixel format and store it to on-chip display ram. this is the default mode. 221kc (24-bit/rgb) : on-chip dither engine will convert input data into 4r-5g-3b format and store it to on-chip display ram. this mode provides the smoothest shades and the most vivid color in the lcd. changing color mode does not affect the content already stored in the display buffer ram. users can use several color modes together in real time. for example, the menu por tion can be painted in 256-color mode for fast update speed, and then switch to 221k-color mode, together with window programming option, and take advantage of built- in dither engine to produce smooth graphics images. l ayout c onsiderations for com signals since the com scanning pulse of uc1682 can be as short as 30s, it is critical to control the rc delay of com signal to minimize distortion of com scanning pulse. for the best image quality, limit the worst case of rc delay of com signal as calculated below. (r row / 2.7+ r com + r out ) x c row < 2s where c row : lcd loading capacitance of one row of pixels. it can be calculated by c lcd /mux-rate, where c lcd is the lcd panel capacitance. r row : ito resistance over one row of pixels within the active area r com : com routing resistance from ic to the active area r out : com output impedance in addition, please make sure | rc max ? rc min | < 0.3 x rc max so that the com distortions on the top of the screen to the bottom of the screen are uniform. l ayout c onsiderations for seg signals excessive seg signal rc decay can cause image dependent changes of medium gray shades and sharply increase of seg direction crosstalk. please limit the worst case of seg signal rc delay as calculated below. (r col /2.7 + r seg ) x c col < 0.5s where c col : lcd loading capacitance of one pixel column. it can be calculated by c lcd / #_of column, c lcd is the lcd panel capacitance. r col : ito resistance over one column of pixels within the active area r seg : seg routing resistance from ic to the active area + seg driver output impedance l ayout c onsiderations for seg signals excessive seg signal rc decay can cause image dependent changes of medium gray shades and sharply increase of seg direction crosstalk. for good image quality, please limit the worst case of seg signal rc delay as calculated below. (r col /2.7 + r seg ) x c col < 0.4s where c col : lcd loading capacitance of one pixel column. it can be calculated by c lcd / #_of column, c lcd is the lcd panel capacitance. r col : ito resistance over one column of pixels within the active area r seg : seg routing resistance from ic to the active area + seg driver output impedance
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 34 es specifications ram w/r pol com1 com2 com3 seg1 seg2 f igure 5: com and seg driving waveform
uc1682 80x104rgb cstn controller-driver revision 0.6 35 h ost i nterface as summarized in the table below, uc1682 supports two parallel bus prot ocols, in either 8-bit or 4-bit bus width, and th ree serial bus protocols. designers can either use parallel bus to achieve high data transfer rate, or use serial bus to create compact lcd modules. bus type 8080 6800 s8 (4wr) s8uc (3wr) s9 (3wr) width 8-bit 4-bit 8- bit 4-bit serial access read/write write only bm[1:0] 10 00 11 01 00 00 01 d[7:6] data 0x data 0x 10 11 1x cs[1:0] chip select cd control/data ? wr0 ___ __ wr _ _ r/w ? wr1 ___ __ rd en ? d[5:4] data ? data ? ? control & data pins d[3:0] data data data data d0=sck, d3=sda * connect unused control pins and data bus pins to v dd or v ss cs disable interface cs init bus state cd 1<=>0 init bus state cd 1=>0 init color mapping reset init bus state reset init color mapping 8-bit 9 ? ? 9 9 9 4-bit 9 ? 9 9 9 9 s8 or s9 9 9 ? 9 9 9 s8uc 9 ? 9 9 9 9 ? cs disable bus interface ? cs can be used to disable bus interface write / read access. ? cd refers to cd transitions within valid cs wind ow. cd = 0 means write command or read status. ? cs / cd sync / reset can be used to initialize bus state machine (like 4 bits / s8 / s9). ? reset can be pin reset / soft reset / power on reset. ? cd can be used to initialize the multi-byte input rgb format to/from on- chip sram mapping. table 3: host interfaces summary p arallel i nterface the timing relationship between uc1682 internal control signal rd, wr and their associated bus actions are shown in the figure below. the display ram read interface is implemented as a two-stage pipe-line. this architecture requires that, every time memory address is modified, either in 8-bi t mode or 4-bit mode, by either set ca, or set ra command, a dummy read cycle needs to be performed before the actual data can propagate through the pipe-line and be read from data port d[7:0]. there is no pipeline in write interface of display ram. data is transferred directly from bus buffer to internal ram on the rising edges of write pulses. 8- bit & 4- bit b us o peration uc1682 supports both 8-bit and 4-bit bus width. the bus width is determined by pin bm[1]. 4-bit bus operation exactly doubles the clock cycles of 8-bit bus operation, msb followed by lsb, including the dummy read, which also requires two clock cycles. the bus cycle of 4-bit mode is reset each time cd pin changes state (when cs is active).
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 36 es specifications l lsb d l d l+k c msb c lsb dummy d c d c+1 m msb m lsb l l+k l+k+1 c c+1 c+2 c+3 m d l d l+k dummy d c d c+1 d c+2 external cd ___ wr __ rd d[7:0] internal write read data latch column address f igure 6: 8 bit parallel interface & related internal signals s erial i nterface uc1682 supports three serial modes, one 4-wire spi mode (s8), one compact 3/4-wire mode (s8uc) and one 3-wire spi mode (s9). bus interface mode is determined by the wiring of the bm[1:0] and d[7:6]. see table in last page for more detail. s8 (4- wire ) i nterface only write operations are su pported in 4-wire serial mode. pin cs[1:0] are used for chip select and bus cycle reset. pin cd is used to determine the content of the data been transferred. during each write cycle, 8 bits of data, msb first, are latched on eight rising sck edges into an 8-bit data holder. if cd=0, the data byte will be decoded as command. if cd=1, this 8-bit will be treated as data and transferred to proper address in the display data ram on the rising edge of the last sck pulse. pin cd is examined when sck is pulled low for the lsb (d0) of each token. cs0 sda sck cd d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 f igure 7.a: 4-wire serial interface (s8) cs0 sda sck cd d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 f igure 7.b: 3/4-wire serial interface (s8uc)
uc1682 80x104rgb cstn controller-driver revision 0.6 37 s8 uc (3/4- wire ) i nterface only write operations are supported in this 3/4-wire serial mode. the data format is identical to s8. however, in addition to cs pins, cd pin transitions will also reset the bus cycle in this mode. so, if cs pins are hardwired to enable chip-select, the bus can work properly with on ly three signal pins. s9 (3- wire ) i nterface only write operations are supported in this 3-wire serial mode. pin cs[1-0] ar e used for chip select and bus cycle reset. on each write cycle, the first bit is cd, which determines the content of the following 8 bits of data, msb first. these 8 command or data bits are latched on rising sck edges into an 8-bit data holder. if cd=0, the data byte will be decoded as command. if cd=1, this 8- bit will be treated as data and transferred to proper address in the display data ram at the rising edge of the last sck pulse. by sending cd information explicitly in the bit stream, control pin cd is not used, and should be connected to either v dd or v ss . the toggle of cs0 or cs1 for each byte of data/command is recommended but optional. cs0 sda sck cd d7 d6 d5 d4 d3 d2 d1 d0 cd d7 d6 f igure 7.c: 3-wire serial interface (s9)
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 38 es specifications h ost interface reference circuit vdd vdd vdd cd decoder cs0 vdd d7-d0 wr bm1 cs1 uc1682 vss rd d7-d0 mpu bm0 gnd wr0(wr) address vcc cd iorq wr1(rd) rst id f igure 8: 8080/8bit parallel mode reference circuit vdd vdd address d3-d0 bm1 decoder vdd cs0 vss rst vcc wr1(rd) cs1 rd bm0 cd uc1682 d3-d0 mpu wr0(wr) wr iorq cd gnd d7 id f igure 9: 8080/4bit parallel mode reference circuit
uc1682 80x104rgb cstn controller-driver revision 0.6 39 vdd vdd vdd wr1(e) cs1 uc1682 cd address mpu decoder wr0(r/w) vdd bm0 vss vcc iorq d7-d0 e d7-d0 r/w cs0 bm1 cd gnd rst id f igure 10: 6800/8bit parallel mode reference circuit vdd vdd vdd cd uc1682 d7 rst cs1 iorq vss bm0 d3-d0 wr0(r/w) decoder e vcc cd gnd wr1(e) bm1 mpu r/w cs0 d3-d0 address vdd id f igure 11: 6800/4bit parallel mode reference circuit
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 40 es specifications vdd vdd vcc bm0 bm1 mpu cd vss uc1682 address cs1 wr1 iorq wr0 cs0 gnd vdd decoder cd sda sda(d3) sck d6 sck(d0) rst id d7 f igure 12: 4-wires spi (s8) serial mode reference circuit vdd vdd vdd cs0 gnd wr0 uc1682 id vss rst vcc sda(d3) sck(d0) vdd sda mpu sck wr1 bm1 bm0 d7 d6 cs1 cd cd f igure 13: 3/4-wires spi (s8uc) seri al mode reference circuit
uc1682 80x104rgb cstn controller-driver revision 0.6 41 vdd vdd vdd vdd vss vcc address uc1682 cs1 mpu cs0 decoder iorq vdd gnd sda(d3) sck sda sck(d0) d7 wr0 wr1 rst id bm1 bm0 f igure 14: 3-wires spi (s9) serial mode reference circuit note ? id pin is for production control. the connection will affect the content of d[7] when using get status command. connect to v dd for ?h? or v ss for ?l?. ? rst pin is optional. when rst pin is not used, connect the pin to v dd .
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 42 es specifications d isplay d ata ram d ata o rganization the input display data (depend on color mode) are stored to a dual port static ram (ram, for display data ram) organized as 80x104x12. after setting ca and ra, the subsequent data write cycles will store t he data for the specified pixel to the proper memory location. please refer to the map in the following page between the relation of com, seg, sram, and various memory control registers. d isplay d ata ram a ccess the display ram is a special purpose dual port ram which allows asynchronous access to both its column and row data. thus, ram can be independently accessed both for host interface and for display operations. d isplay d ata ram a ddressing a host interface (hi) memory access operation starts with specifying row address (ra) and column address (ca) by issuing set row address and set column address commands. if wrap-around (wa, ac[0]) is off (0), ca will stop incrementing after reaching the end of row (103), and system programmers need to set the values of ra and ca explicitly. if wa is on (1), when ca reaches the end of a row, ca will be reset to 0 and ra will increment or decrement, depending on the setting of row increment direction (rid, ac[2]). when ra reaches the boundary of ra m (i.e. ra = 0 or 79), ra will be wrapped around to the other end of ram and continue. mx i mplementation column mirroring (mx) is implemented by selecting either (ca) or (103?ca) as the ram column address. changing mx affects the data written to the ram. since mx has no effect on the data already stored in ram, changing mx does not have immediate effect on the displayed pattern. to refresh the display, refresh the data stored in ram after setting mx. r ow m apping com electrode scanning orders are not affected by start line (sl), fixed line (fl) or mirror y (my, lc[3]). visually, register sl having a non- zero value is equivalent to scrolling the lcd display up or down (depends on my) by sl rows. ram a ddress g eneration the mapping of the data stored in the display sram and the scanning com electrodes can be obtained by combining the fixed com scanning sequence and the following ram address generation formula. when fl=0, during the display operation, the ram line address generation can be mathematically represented as following: for the 1 st line period of each field line = sl otherwise line = mod( line +1, 80) where mod is the modular operator, and line is the bit slice line address of ram to be outputted to seg drivers. line 0 corresponds to the first bit- slice of data in ram. the above line generation formula produces the ?loop around? effect as it effectively resets line to 0 when line+1 reaches 80 . effects such as scrolling can be emulated by changing sl dynamically. my i mplementation row mirroring (my) is implemented by reversing the mapping order between com electrodes and ram, i.e. the mathematical address generation formula becomes: for the 1 st line period of each field line = mod( sl + mux-1 , 80 ) where mux = cen + 1 otherwise line = mod( line-1 , 80 ) visually, the effect of my is equivalent to flipping the display upside down. the data stored in display ram are not affected by my.
uc1682 80x104rgb cstn controller-driver revision 0.6 43 w indow program window program is designed for data write in a specified window range of sram address. the procedure should start with window boundary registers setting ( wpp0 , wpp1 , wpc0 and wpc1 ) and then enable ac[4]. after ac[4] sets, data can be written to sram within the window address range which is specified by ( wpp0, wpc0 ) and ( wpp1, wpc1 ). ac[4] should be cleared after any modification of window boundary registers and then set again in order to initialize another window program. the data write direction will be determined by ac[2:0] and mx settings. when ac[0]=1, the data write can be consecutive within the range of the specified window. ac[1] will control the data write in either column or row direction. ac[2] will result the data write starting either from row wpp0 or wpp1 . mx is for the initial column address either from wpc0 to wpc1 or from ( mc- wpc0 to mc-wpc1 ). example1: example 2: ac[2:0] = 001 mx=0 ac[2:0] = 111 mx = 0 column 0 103 row 79 (wpp0, wpc0) (wpp1,wpc1) (wpp0, wpc0) (wpp1,wpc1)
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 44 es specifications row ram adderss sl=0 sl=16 sl=0 sl=16 00h com1 com65 com80 com16 01h com2 com66 com79 com15 02h com3 com67 com78 com14 03h com4 com68 com77 com13 04h com5 com69 com76 com12 05h com6 com70 com75 com11 06h com7 com71 com74 com10 07h com8 com72 com73 com9 08h com9 com73 com72 com8 09h com10 com74 com7 0ah com11 com75 com6 0bh com12 com76 com5 0ch com13 com77 com4 0dh com14 com78 com3 0eh com15 com79 com2 0fh com16 com80 com1 10h com17 com1 com80 11h com18 com2 com79 12h com19 com3 com78 13h com20 com4 com77 14h com21 com5 com76 15h com22 com6 com75 16h com23 com7 com74 17h com24 com8 com73 18h com25 com9 com72 19h com26 com10 1ah com27 com11 1bh com28 com12 1ch com29 com13 38h com40 39h com39 3ah com38 3bh com37 3ch com36 3dh com35 3eh com34 3fh com33 40h com32 41h com31 42h com30 43h com29 44h com28 45h com27 46h com26 47h com25 48h com24 49h com23 4ah com22 4bh com76 com60 com5 com21 4ch com77 com61 com4 com20 4dh com78 com62 com3 com19 4eh com79 com63 com2 com18 4fh com80 com64 com1 com17 0 seg1 seg2 seg3 seg4 seg5 seg308 seg309 seg310 seg311 seg312 1 seg312 seg311 seg310 seg309 seg308 seg5 seg4 seg3 seg2 seg1 my=1 my=0 mx example for memory mapping: let mx = 0, my = 0, sl = 0, lc[7:6] = 10b ( rrrrr-gggggg-bbbbb, 56k color ), according to the data shown in the above table (r: 11111b, g: 111111b, b: 11111b): ? 1 st byte write data: 11111111b ? 2 nd byte write data: 11111111b
uc1682 80x104rgb cstn controller-driver revision 0.6 45 r eset & p ower m anagement t ypes of r eset uc1682 has two different types of reset: power-on-reset and system-reset . power-on-reset is performed right after v dd is connected to power. power-on-reset will first wait for about 5~10ms, dependi ng on the time required for v dd to stabilize, and then trigger the system reset . system reset can also be activated by software command or by connecting rst pin to ground. in the following discussions, reset means system reset . r eset s tatus when uc1682 enters reset sequence: ? operation mode will be ?reset? ? system status bits rs and bz will stay as ?1? until the reset process is completed. when rs=1, the ic will only respond to read status command. all other commands are ignored. ? all control registers are reset to default values. refer to control registers for details of their default values. o peration m odes uc1682 has three operating modes (om): reset, normal, sleep. mode reset sleep normal om 00 10 11 host interface active active active clock off off on lcd drivers off off on charge pump off off on draining circuit on off off table 4: operating modes c hanging o peration m ode in addition to power-on-reset, two commands will initiate om transitions: set display enable , and system reset . when dc[2] is modified by set display enable , om will be updated automatica lly. there is no other action required to enter sleep mode. for maximum energy utilization, sleep mode is designed to retain charges stored in external capacitors c b0 , c b1 , and c l . to drain these capacitors, use reset command to activate the on- chip draining circuit. action mode om set driver enable to ?0? sleep 10 set driver enable to ?1? normal 11 reset command or rst_ pin pulled ?l? power on reset reset 00 table 5: om changes even though uc1682 consumes very little energy in sleep mode (typically 5ua or less); however, since all capacitors are still charged, the leakage through com drivers may damage the lcd over the long term. it is therefore recommended to use sleep mode only for brief display off operations, such as full-frame screen updates, and to use reset for extended screen off operations. e xiting s leep m ode uc1682 contains internal logic to check whether v lcd and v bias are ready before releasing com and seg drivers from their idle states. when exiting sleep or reset mode, com and seg drivers will not be activated until uc1682 internal voltage sources are restored to their proper values.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 46 es specifications p ower -u p s equence uc1682 power-up sequence is simplified by built-in ?power ready? flags and the automatic invocation of system-reset command after power-on-reset . system programmers are onl y required to wait 5~ 10 ms before the cpu starting to issue commands to uc1682. no additional time sequences are required between enabling the charge pump, turning on the display drivers, writing to ram or any other commands. however, while turning on v dd , v dd2/3 should be started not later than v dd . delay allowance between v dd and v dd2/3 is illustrated as figure 15-1. p ower -d own s equence to prevent the charge stored in capacitors c bx+ , c bx? , and c l from damaging the lcd, when v dd is switched off, use reset mode to enable the built-in draining circuit and disch arge these capacitors. the draining resistor is 1k ? for both v lcd and v b+ . it is recommended to wait 3 x rc for v lcd and 1.5 x rc for v b+ . for example, if c l is 15nf, then the draining time required for v lcd is 0.5~1ms. when internal v lcd is not used, uc1682 will not drain v lcd during reset. system designers need to make sure external v lcd source is properly drained off before turning off v dd . turn on vdd set lcd bias ratio (br) set potential meter (pm) set display enable wait 5~10 ms set otpc[4] ( ignore otp value when ?l? ) figure 15: reference power-up sequence turn off vdd reset command wait ~1 ms figure 16: reference power-down sequence figure 15-1: delay allowance and power off-on sequence t delay > 0 s v dd2/3 > 2.4v v dd > 1.8v v dd2/3 > v dd 10 s < t 1 , t 2 < 10 ms t 1 t 2 t wait > 50 ms t f < 10 ms
uc1682 80x104rgb cstn controller-driver revision 0.6 47 s ample p ower m anagement c ommand s equences the following tables are examples of command sequence for power-up, power-down and display on/off operations. these are only to demonstrate some ? typical, generic ? scenarios. designer s are encouraged to study related sections of the datasheet and find out what the best parameters and control sequences are for their specific design needs. c/d the type of the interface cycle. it can be either command (0) or data (1) w/r the direction of dataflow of the cycle. it can be either write (0) or read (1). type r equired: these items are required c ustomer: these items are not necessary if cu stomer parameters are the same as default a dvanced: we recommend new users to skip these commands and use default values. o ptional: these commands depend on what users want to do. p ower -u p type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r ? ? ? ? ? ? ? ? ? ? automatic power-on reset. wait 5~10ms after v dd is on r 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 (37) set otp operation control. (double-type command) ignore otp value c 0 0 0 0 1 0 0 1 # # (5) set temp. compensation c 0 0 1 1 0 0 0 # # # (20) set lcd mapping set up lcd format specific parameters, mx, my, etc. a 0 0 1 0 1 0 0 0 # # (15) set line rate c 0 0 1 1 0 1 0 1 # # (22) set color mode fine tune for power, flicker, contrast, and shading. c 0 0 1 1 1 0 1 0 # # (26) set lcd bias ratio r 0 0 0 0 1 # 0 # 0 # 0 # 0 # 0 # 0 # 1 # (11) set v bias potentiometer lcd specific operating voltage setting o 1 . . 1 0 . . 0 # . . # # . . # # . . # # . . # # . . # # . . # # . . # # . . # write display ram set up display image r 0 0 1 0 1 0 1 1 1 1 (18) set display enable p ower -d own type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r 0 0 1 1 1 0 0 0 1 0 (23) system reset r ? ? ? ? ? ? ? ? ? ? draining capacitor wait ~1ms before v dd off b rief d isplay -off type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r 0 0 1 0 1 0 1 1 1 0 (18) set display disable c 1 . . 1 0 . . 0 # . . # # . . # # . . # # . . # # . . # # . . # # . . # # . . # write display ram set up display image (image update is optional. data in the ram is retained through the sleep state.) r 0 0 1 0 1 0 1 1 1 1 (18) set display enable * this is only recommended for very brief display off (under 10ms). if image becomes unstable use the extended display off approach shown below.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 48 es specifications e xtended d isplay -off type c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 chip action comments r 0 0 1 1 1 0 0 0 1 0 (23) system reset. c b1 , c b1 , c lcd discharged. ? ? ? ? ? ? ? ? ? ? ? extended display off z z z z . . . ? ? ? ? ? ? ? ? ? ? ? system waking up r repeat power-up sequence repeat power up register setting sequence c 1 . . 1 0 . . 0 # . . # # . . # # . . # # . . # # . . # # . . # # . . # # . . # write display ram set up display image (image update is optional. data in the ram is retained through the reset state.) r 0 0 1 0 1 0 1 1 1 1 (18) set display enable * the sequence is basically the same as the power up sequence, except power-on reset is replaced by system reset command, and an extended idle time in between.
uc1682 80x104rgb cstn controller-driver revision 0.6 49 a bsolute m aximum r atings in accordance with iec134, note 1, 2 and 3. symbol parameter min. max. unit v dd logic supply voltage -0.3 +4.0 v v dd2 lcd generator supply voltage -0.3 +4.0 v v dd3 analog circuit supply voltage -0.3 +4.0 v v lcd lcd driving voltage (-25 o c ~ +75 o c) -0.3 +12.0 v v in digital input signal -0.4 v dd + 0.5 v t opr operating temperature range -30 +85 o c t str storage temperature -55 +125 o c notes 1. v dd based on v ss = 0v 2. stress beyond ranges listed above may cause permanent damages to the device.
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 50 es specifications s pecifications dc c haracteristics symbol parameter conditions min. typ. max. unit v dd supply for digital circuit 1.8 3.3 v v dd2/3 supply for bias & pump 2.4 3.3 v v lcd charge pump output v dd2/3 2.4v, 25 o c 9.9 10.5 v v d lcd data voltage v dd2/3 2.4v, 25 o c 0.9 1.5 v v il input logic low 0.2v dd v v ih input logic high 0.8v dd v v ol output logic low 0.2v dd v v oh output logic high 0.8v dd v i il input leakage current 1.5 a c in input capacitance 5 10 pf c out output capacitance 5 10 pf r 0(seg) seg output impedance v lcd = 9.9v 1.5 3.0 k ? r 0(com) com output impedance v lcd = 9.9v 2.0 4.0 k ? f line average line rate lc[4:3] = 11b 18.4 20 22.4 klps note: when v dd < 2.0, letting v il = 0 and v ih = v dd is recommended. p ower c onsumption v dd = 2.8v, bias ratio = 8, pm = 142, v lcd = 9.9v, line rate =10b, pl = 11b, mr =80, bus mode =6800, c l = 5nf~50nf, c b = 2f. all seg/com outputs are open-circuit. display pattern conditions typ. (a) max. (a) all-off bus = idle 665 2000 2-pixel checker bus = idle 860 2000 v lcd bus = idle (standby current) - 5
uc1682 80x104rgb cstn controller-driver revision 0.6 51 ac c haracteristics f igure 17: parallel bus timing characteristics (for 8080 mcu) (2.5v v dd < 3.3v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as80 t ah80 cd address setup time address hold time 0 15 ? ns t cy80 system cycle time 8 bits bus (read) (write) 4 bits bus (read) (write) 140 80 140 80 ? ns t pwr80 wr1 pulse width 8 bits (read) 4 bits 70 70 ? ns t pww80 wr0 pulse width 8 bits (write) 4 bits 40 40 ? ns t hpw80 wr0, wr1 high pulse width 8 bits bus (read) (write) 4 bits bus (read) (write) 70 40 70 40 ? ns t ds80 t dh80 d0~d7 data setup time data hold time 30 15 ? ns t acc80 t od80 read access time output disable time c l = 100pf ? 25 80 40 ns t c ssa80 t cssd80 t csh80 cs1/cs0 chip select setup time 10 10 20 ns cd t as80 t ah80 cs0 cs1 t cssa80 t cy80 t csh80 t cssd80 t pwr80 , t pww80 t hpw80 wr0 wr1 t ds80 t dh80 write d[7:0] t acc80 t od80 read d[7:0]
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 52 es specifications (1.8v v dd < 2.5v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as80 t ah80 cd address setup time address hold time 0 30 ? ns t cy80 system cycle time 8 bits bus (read) (write) 4 bits bus (read) (write) 280 160 280 160 ? ns t pwr80 wr1 pulse width 8 bits (read) 4 bits (read) 140 140 ? ns t pww80 wr0 pulse width 8 bits (write) 4 bits (write) 80 80 ? ns t hpw80 wr0, wr1 high pulse width 8 bits bus (read) (write) 4 bits bus (read) (write) 140 80 140 80 ? ns t ds80 t dh80 d0~d7 data setup time data hold time 60 30 ? ns t acc80 t od80 read access time output disable time c l = 100pf - 50 160 80 ns t cssa80 t cssd80 t csh80 cs1/cs0 chip select setup time 20 20 40 ns
uc1682 80x104rgb cstn controller-driver revision 0.6 53 f igure 18: parallel bus timing characteristics (for 6800 mcu) (2.5v v dd < 3.3v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as68 t ah68 cd address setup time address hold time 0 20 ? ns t cy68 system cycle time 8 bits bus (read) (write) 4 bits bus (read) (write) 140 80 140 80 ? ns t pwr68 wr1 pulse width 8 bits (read) 4 bits 70 70 ? ns t pww68 pulse width 8 bits (write) 4 bits 40 40 ? ns t lpw68 low pulse width 8 bits bus (read) (write) 4 bits bus (read) (write) 70 40 70 40 ? ns t ds68 t dh68 d0~d7 data setup time data hold time 30 15 ? ns t acc68 t od68 read access time output disable time c l = 100pf ? 25 80 40 ns t cssa68 t cssd68 t csh68 cs1/cs0 chip select setup time 10 10 20 ns cd t as68 t ah68 cs0 cs1 t cssa68 t cy68 t csh68 t cssd68 t pwr68 , t pww68 t lpw68 wr1 t ds68 t dh68 write d[7:0] t acc68 t od68 read d[7:0]
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 54 es specifications (1.8v v dd < 2.5v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as68 t ah68 cd address setup time address hold time 0 40 ? ns t cy68 system cycle time 8 bits bus (read) (write) 4 bits bus (read) (write) 280 160 280 160 ? ns t pwr68 wr1 pulse width 8 bits (read) 4 bits 140 140 ? ns t pww68 pulse width 8 bits (write) 4 bits 80 80 ? ns t lpw68 low pulse width 8 bits bus (read) (write) 4 bits bus (read) (write) 140 80 140 80 ? ns t ds68 t dh68 d0~d7 data setup time data hold time 60 30 ? ns t acc68 t od68 read access time output disable time c l = 100pf - 50 160 80 ns t cssa68 t cssd68 t csh68 cs1/cs0 chip select setup time 20 20 40 ns
uc1682 80x104rgb cstn controller-driver revision 0.6 55 f igure 19: serial bus timing characteristics (for s8) (2.5v v dd < 3.3v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t ass8 address setup time 0 ? ns t ahs8 cd address hold time 15 ? ns t cys8 system cycle time 80 ? ns t lpws8 low pulse width 35 ? ns t hpws8 sck high pulse width 35 ? ns t dss8 t dhs8 sda data setup time data hold time 30 20 ? ns t cssas8 t cssds8 t cshs8 cs1/cs0 chip select setup time 10 10 20 ns (1.8v v dd < 2.5v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t ass8 address setup time 0 ? ns t ahs8 cd address hold time 30 ? ns t cys8 system cycle time 160 ? ns t lpws8 low pulse width 70 ? ns t hpws8 sck high pulse width 70 ? ns t dss8 t dhs8 sda data setup time data hold time 60 40 ? ns t cssas8 t cssds8 t cshs8 cs1/cs0 chip select setup time 20 20 40 ns cd t ass8 t ahs8 cs0 cs1 t cssas8 t cys8 t cshs8 t cssds8 t lpws8 t hpws8 sck t dss8 t dhs8 sda
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 56 es specifications f igure 20: serial bus timing characteristics (for s9) (2.5v v dd < 3.3v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t cys9 system cycle time 80 ? ns t lpws9 low pulse width 35 ? ns t hpws9 sck high pulse width 35 ? ns t dss9 t dhs9 sda data setup time data hold time 30 20 ? ns t cssas9 t cssds9 t cshs9 cs1/cs0 chip select setup time 10 10 20 ns (1.8v v dd < 2.5v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t cys9 system cycle time 160 ? ns t lpws9 low pulse width 70 ? ns t hpws9 sck high pulse width 70 ? ns t dss9 t dhs9 sda data setup time data hold time 60 40 ? ns t cssas9 t cssds9 t cshs9 cs1/cs0 chip select setup time 20 20 40 ns cs0 cs1 t css9 t cys9 t cshs9 t cssds9 t wls9 t whs9 sck t dss9 t dhs9 sda
uc1682 80x104rgb cstn controller-driver revision 0.6 57 rst t rw f igure 21: reset characteristics (1.8v v dd < 3.3v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t rw rst reset low pulse width 500 ? s
u ltra c hip high-voltage mixed-signal ic ? 1999 ~ 2003 58 es specifications p hysical d imensions p ad c oordinates d ie s ize : 13.944mm x 1.494mm d ie t hickness : 0.5mm b ump height : 17m 1m (within die) m inimum b ump pitch : seg: 41.5m (typ.) com: 50.0m (typ.) m inimum b ump g ap : 17m (typ.) c oordinate origin : chip center p ad reference : pad center (drawing and coordinates are for the circuit/bump view.)
uc1682 80x104rgb cstn controller-driver revision 0.6 59 a lignment m ark i nformation (0,0) d-left mark d-right mark u-left mark u-right mark 1 2 3 s hape of the alignment mark : c oordinates : u-left mark u-right mark x y x y 1 -6887.1 615.7 6853.2 608.5 2 -6879.1 606.5 6882.4 589.2 3 -6846.2 598.5 6858.1 613.4 d-left mark d-right mark x y x y 1 -5690.3 -612.1 5535.4 -612.1 2 -5678.3 -667.2 5547.4 -667.2 3 -5701.8 -633.7 5523.9 -633.7 4 -5666.8 -645.7 5558.9 -645.7 c -5684.3 -639.7 5541.4 -639.7 1 2 3 n ote : a lignment mark is on metal3 under passivation. f or n on -otp p rocess c ross -s ection f or otp p rocess c ross -s ection t op m etal and p assivation : metal3 / 9k ? sio2 / 5k ? ? ? sion / (tbd)k ?
u ltra c hip high-voltage mixed-signal ic ?1999~2003 60 es specifications pi i nformation p i t hickness : 3.6 0.4 m m inimum s eparation of b ump t o e dge of p olyimide l ayer : 20 m
uc1682 80x104rgb cstn controller-driver revision 0.6 61 p ad c oordinates # pad name x y w h 1 dummy -6867.9 649.7 85 50 2 com2 -6867.4 570.3 95 33 3 com4 -6867.4 520.3 95 33 4 com6 -6867.4 470.3 95 33 5 com8 -6867.4 420.3 95 33 6 com10 -6867.4 370.3 95 33 7 com12 -6867.4 320.3 95 33 8 com14 -6867.4 270.3 95 33 9 com16 -6867.4 220.3 95 33 10 com18 -6867.4 170.3 95 33 11 com20 -6867.4 120.3 95 33 12 com22 -6867.4 70.3 95 33 13 com24 -6867.4 20.3 95 33 14 com26 -6867.4 -29.8 95 33 15 com28 -6867.4 -79.8 95 33 16 com30 -6867.4 -129.8 95 33 17 com32 -6867.4 -179.8 95 33 18 com34 -6867.4 -229.8 95 33 19 com36 -6867.4 -279.8 95 33 20 com38 -6867.4 -329.8 95 33 21 com40 -6867.4 -379.8 95 33 22 com42 -6867.4 -429.8 95 33 23 com44 -6867.4 -479.8 95 33 24 com46 -6867.4 -529.8 95 33 25 com48 -6867.4 -579.8 95 33 26 dummy -6867.9 -654.4 85 50 27 com50 -6479.6 -642.4 33 95 28 com52 -6429.6 -642.4 33 95 29 com54 -6379.6 -642.4 33 95 30 com56 -6329.6 -642.4 33 95 31 com58 -6279.6 -642.4 33 95 32 com60 -6229.6 -642.4 33 95 33 com62 -6179.6 -642.4 33 95 34 com64 -6129.6 -642.4 33 95 35 com66 -6079.6 -642.4 33 95 36 com68 -6029.6 -642.4 33 95 37 com70 -5979.6 -642.4 33 95 38 com72 -5929.6 -642.4 33 95 39 com74 -5879.6 -642.4 33 95 40 com76 -5829.6 -642.4 33 95 41 com78 -5779.6 -642.4 33 95 42 com80 -5729.6 -642.4 33 95 43 d7 -5481.6 -645.4 50 80 44 vddx -5402.3 -645.4 50 80 45 d6 -5323.8 -645.4 50 80 46 d5 -5093.8 -645.4 50 80 47 d4 -4863.8 -645.4 50 80 48 d3 -4633.8 -645.4 50 80 49 d2 -4403.8 -645.4 50 80 50 d1 -4173.8 -645.4 50 80 51 d0 -3943.8 -645.4 50 80 52 vbias -3706.0 -645.4 50 80 53 rst_ -3501.3 -645.4 50 80 54 cs1 -3407.5 -645.4 50 80 55 vddx -3333.2 -645.4 50 80 56 cs0 -3256.9 -645.4 50 80 57 cd -3173.6 -645.4 50 80 58 wr0 -3086.1 -645.4 50 80 59 vddx -3009.0 -645.4 50 80 60 wr1 -2930.4 -645.4 50 80 # pad name x y w h 61 bm0 -2840.0 -645.4 50 80 62 vddx -2760.8 -645.4 50 80 63 bm1 -2681.9 -645.4 50 80 64 tst4 -2593.9 -645.4 50 80 65 tst4 -2523.9 -645.4 50 80 66 tp5 -2195.0 -645.4 50 80 67 tst2 -2124.8 -645.4 50 80 68 tp4 -1800.8 -645.4 50 80 69 tp3 -1727.1 -645.4 50 80 70 tp2 -1657.1 -645.4 50 80 71 tp1 -1587.1 -645.4 50 80 72 id -1480.7 -645.4 50 80 73 vss -1391.6 -645.4 50 80 74 vss -1311.6 -645.4 50 80 75 vss -1231.6 -645.4 50 80 76 vss -1151.6 -645.4 50 80 77 vss -1071.6 -645.4 50 80 78 vss -991.5 -645.4 50 80 79 vss2 -911.5 -645.4 50 80 80 vss2 -831.5 -645.4 50 80 81 vss2 -751.5 -645.4 50 80 82 vss2 -671.5 -645.4 50 80 83 vss2 -591.5 -645.4 50 80 84 vdd3 -511.5 -645.4 50 80 85 vdd3 -431.5 -645.4 50 80 86 vdd3 -351.5 -645.4 50 80 87 vdd3 -275.1 -645.4 50 80 88 vdd2 -97.5 -645.4 50 80 89 vdd2 -17.5 -645.4 50 80 90 vdd2 62.5 -645.4 50 80 91 vdd2 141.1 -645.4 50 80 92 vdd2 219.5 -645.4 50 80 93 vdd 493.0 -645.4 50 80 94 vdd 573.0 -645.4 50 80 95 vdd 653.0 -645.4 50 80 96 vdd 733.0 -645.4 50 80 97 vdd 813.0 -645.4 50 80 98 vdd 893.0 -645.4 50 80 99 vb0+ 972.9 -645.4 50 80 100 vb0+ 1042.9 -645.4 50 80 101 vb0+ 1112.9 -645.4 50 80 102 vb0+ 1182.9 -645.4 50 80 103 vb0+ 1252.9 -645.4 50 80 104 vb0+ 1475.7 -645.4 50 80 105 vb0+ 1546.0 -645.4 50 80 106 vb0+ 1616.0 -645.4 50 80 107 vb0+ 1686.0 -645.4 50 80 108 sb0+ 1756.0 -645.4 50 80 109 vb1+ 1974.9 -645.4 50 80 110 vb1+ 2044.9 -645.4 50 80 111 vb1+ 2114.9 -645.4 50 80 112 vb1+ 2184.9 -645.4 50 80 113 vb1+ 2254.9 -645.4 50 80 114 vb1+ 2477.7 -645.4 50 80 115 vb1+ 2548.0 -645.4 50 80 116 vb1+ 2618.0 -645.4 50 80 117 vb1+ 2688.0 -645.4 50 80 118 sb1+ 2758.0 -645.4 50 80 119 vb1- 2976.9 -645.4 50 80 120 vb1- 3046.9 -645.4 50 80
u ltra c hip high-voltage mixed-signal ic ?1999~2003 62 es specifications # pad name x y w h 121 vb1- 3116.9 -645.4 50 80 122 vb1- 3186.9 -645.4 50 80 123 vb1- 3256.9 -645.4 50 80 124 vb1- 3479.7 -645.4 50 80 125 vb1- 3550.0 -645.4 50 80 126 vb1- 3620.0 -645.4 50 80 127 vb1- 3690.0 -645.4 50 80 128 sb1- 3760.0 -645.4 50 80 129 vb0- 3978.9 -645.4 50 80 130 vb0- 4048.9 -645.4 50 80 131 vb0- 4118.9 -645.4 50 80 132 vb0- 4188.9 -645.4 50 80 133 vb0- 4258.9 -645.4 50 80 134 vb0- 4481.7 -645.4 50 80 135 vb0- 4552.0 -645.4 50 80 136 vb0- 4622.0 -645.4 50 80 137 vb0- 4692.0 -645.4 50 80 138 sb0- 4762.0 -645.4 50 80 139 vlcdin 5118.4 -645.4 50 80 140 vlcdin 5188.7 -645.4 50 80 141 vlcdout 5258.7 -645.4 50 80 142 vlcdout 5328.7 -645.4 50 80 143 com79 5610.6 -642.4 33 95 144 com77 5660.6 -642.4 33 95 145 com75 5710.6 -642.4 33 95 146 com73 5760.6 -642.4 33 95 147 com71 5810.6 -642.4 33 95 148 com69 5860.6 -642.4 33 95 149 com67 5910.6 -642.4 33 95 150 com65 5960.6 -642.4 33 95 151 com63 6010.6 -642.4 33 95 152 com61 6060.6 -642.4 33 95 153 com59 6110.6 -642.4 33 95 154 com57 6160.6 -642.4 33 95 155 com55 6210.6 -642.4 33 95 156 com53 6260.6 -642.4 33 95 157 com51 6310.6 -642.4 33 95 158 com49 6360.6 -642.4 33 95 159 dummy 6868.1 -658.7 85 50 160 com47 6867.6 -594.9 95 33 161 com45 6867.6 -544.9 95 33 162 com43 6867.6 -494.9 95 33 163 com41 6867.6 -444.9 95 33 164 com39 6867.6 -394.9 95 33 165 com37 6867.6 -344.9 95 33 166 com35 6867.6 -294.9 95 33 167 com33 6867.6 -244.9 95 33 168 com31 6867.6 -194.9 95 33 169 com29 6867.6 -144.9 95 33 170 com27 6867.6 -94.9 95 33 171 com25 6867.6 -44.9 95 33 172 com23 6867.6 5.1 95 33 173 com21 6867.6 55.1 95 33 174 com19 6867.6 105.1 95 33 175 com17 6867.6 155.1 95 33 176 com15 6867.6 205.1 95 33 177 com13 6867.6 255.1 95 33 178 com11 6867.6 305.1 95 33 179 com9 6867.6 355.1 95 33 180 com7 6867.6 405.1 95 33 181 com5 6867.6 455.1 95 33 182 com3 6867.6 505.1 95 33 183 com1 6867.6 555.1 95 33 # pad name x y w h 184 dummy 6868.1 649.7 85 50 185 seg1 6538.0 628.6 24.5 123 186 seg2 6496.5 628.6 24.5 123 187 seg3 6455.0 628.6 24.5 123 188 seg4 6413.5 628.6 24.5 123 189 seg5 6372.0 628.6 24.5 123 190 seg6 6330.5 628.6 24.5 123 191 seg7 6289.0 628.6 24.5 123 192 seg8 6247.5 628.6 24.5 123 193 seg9 6206.0 628.6 24.5 123 194 seg10 6164.5 628.6 24.5 123 195 seg11 6123.0 628.6 24.5 123 196 seg12 6081.5 628.6 24.5 123 197 seg13 6040.0 628.6 24.5 123 198 seg14 5998.5 628.6 24.5 123 199 seg15 5957.0 628.6 24.5 123 200 seg16 5915.5 628.6 24.5 123 201 seg17 5874.0 628.6 24.5 123 202 seg18 5832.5 628.6 24.5 123 203 seg19 5791.0 628.6 24.5 123 204 seg20 5749.5 628.6 24.5 123 205 seg21 5708.0 628.6 24.5 123 206 seg22 5666.5 628.6 24.5 123 207 seg23 5625.0 628.6 24.5 123 208 seg24 5583.5 628.6 24.5 123 209 seg25 5542.0 628.6 24.5 123 210 seg26 5500.5 628.6 24.5 123 211 seg27 5459.0 628.6 24.5 123 212 seg28 5417.5 628.6 24.5 123 213 seg29 5376.0 628.6 24.5 123 214 seg30 5334.5 628.6 24.5 123 215 seg31 5293.0 628.6 24.5 123 216 seg32 5251.5 628.6 24.5 123 217 seg33 5210.0 628.6 24.5 123 218 seg34 5168.5 628.6 24.5 123 219 seg35 5127.0 628.6 24.5 123 220 seg36 5085.5 628.6 24.5 123 221 seg37 5044.0 628.6 24.5 123 222 seg38 5002.5 628.6 24.5 123 223 seg39 4961.0 628.6 24.5 123 224 seg40 4919.5 628.6 24.5 123 225 seg41 4878.0 628.6 24.5 123 226 seg42 4836.5 628.6 24.5 123 227 seg43 4795.0 628.6 24.5 123 228 seg44 4753.5 628.6 24.5 123 229 seg45 4712.0 628.6 24.5 123 230 seg46 4670.5 628.6 24.5 123 231 seg47 4629.0 628.6 24.5 123 232 seg48 4587.5 628.6 24.5 123 233 seg49 4546.0 628.6 24.5 123 234 seg50 4504.5 628.6 24.5 123 235 seg51 4463.0 628.6 24.5 123 236 seg52 4421.5 628.6 24.5 123 237 seg53 4380.0 628.6 24.5 123 238 seg54 4338.5 628.6 24.5 123 239 seg55 4297.0 628.6 24.5 123 240 seg56 4255.5 628.6 24.5 123 241 seg57 4214.0 628.6 24.5 123 242 seg58 4172.5 628.6 24.5 123 243 seg59 4131.0 628.6 24.5 123 244 seg60 4089.5 628.6 24.5 123 245 seg61 3962.3 628.6 24.5 123 246 seg62 3920.8 628.6 24.5 123
uc1682 80x104rgb cstn controller-driver revision 0.6 63 # pad name x y w h 247 seg63 3879.3 628.6 24.5 123 248 seg64 3837.8 628.6 24.5 123 249 seg65 3796.3 628.6 24.5 123 250 seg66 3754.8 628.6 24.5 123 251 seg67 3713.3 628.6 24.5 123 252 seg68 3671.8 628.6 24.5 123 253 seg69 3630.3 628.6 24.5 123 254 seg70 3588.8 628.6 24.5 123 255 seg71 3547.3 628.6 24.5 123 256 seg72 3505.8 628.6 24.5 123 257 seg73 3464.3 628.6 24.5 123 258 seg74 3422.8 628.6 24.5 123 259 seg75 3381.3 628.6 24.5 123 260 seg76 3339.8 628.6 24.5 123 261 seg77 3298.3 628.6 24.5 123 262 seg78 3256.8 628.6 24.5 123 263 seg79 3215.3 628.6 24.5 123 264 seg80 3173.8 628.6 24.5 123 265 seg81 3132.3 628.6 24.5 123 266 seg82 3090.8 628.6 24.5 123 267 seg83 3049.3 628.6 24.5 123 268 seg84 3007.8 628.6 24.5 123 269 seg85 2966.3 628.6 24.5 123 270 seg86 2924.8 628.6 24.5 123 271 seg87 2883.3 628.6 24.5 123 272 seg88 2841.8 628.6 24.5 123 273 seg89 2800.3 628.6 24.5 123 274 seg90 2758.8 628.6 24.5 123 275 seg91 2717.3 628.6 24.5 123 276 seg92 2675.8 628.6 24.5 123 277 seg93 2634.3 628.6 24.5 123 278 seg94 2592.8 628.6 24.5 123 279 seg95 2551.3 628.6 24.5 123 280 seg96 2509.8 628.6 24.5 123 281 seg97 2468.3 628.6 24.5 123 282 seg98 2426.8 628.6 24.5 123 283 seg99 2385.3 628.6 24.5 123 284 seg100 2343.8 628.6 24.5 123 285 seg101 2302.3 628.6 24.5 123 286 seg102 2260.8 628.6 24.5 123 287 seg103 2219.3 628.6 24.5 123 288 seg104 2177.8 628.6 24.5 123 289 seg105 2136.3 628.6 24.5 123 290 seg106 2094.8 628.6 24.5 123 291 seg107 2053.3 628.6 24.5 123 292 seg108 2011.8 628.6 24.5 123 293 seg109 1970.3 628.6 24.5 123 294 seg110 1928.8 628.6 24.5 123 295 seg111 1887.3 628.6 24.5 123 296 seg112 1845.8 628.6 24.5 123 297 seg113 1804.3 628.6 24.5 123 298 seg114 1762.8 628.6 24.5 123 299 seg115 1721.3 628.6 24.5 123 300 seg116 1679.8 628.6 24.5 123 301 seg117 1638.3 628.6 24.5 123 302 seg118 1596.8 628.6 24.5 123 303 seg119 1555.3 628.6 24.5 123 304 seg120 1513.8 628.6 24.5 123 305 seg121 1472.3 628.6 24.5 123 306 seg122 1430.8 628.6 24.5 123 307 seg123 1389.3 628.6 24.5 123 308 seg124 1347.8 628.6 24.5 123 309 seg125 1306.3 628.6 24.5 123 # pad name x y w h 310 seg126 1264.8 628.6 24.5 123 311 seg127 1223.3 628.6 24.5 123 312 seg128 1181.8 628.6 24.5 123 313 seg129 1140.3 628.6 24.5 123 314 seg130 1098.8 628.6 24.5 123 315 seg131 1057.3 628.6 24.5 123 316 seg132 1015.8 628.6 24.5 123 317 seg133 974.3 628.6 24.5 123 318 seg134 932.8 628.6 24.5 123 319 seg135 891.3 628.6 24.5 123 320 seg136 849.8 628.6 24.5 123 321 seg137 808.3 628.6 24.5 123 322 seg138 766.8 628.6 24.5 123 323 seg139 725.3 628.6 24.5 123 324 seg140 683.8 628.6 24.5 123 325 seg141 642.3 628.6 24.5 123 326 seg142 600.8 628.6 24.5 123 327 seg143 559.3 628.6 24.5 123 328 seg144 517.8 628.6 24.5 123 329 seg145 476.3 628.6 24.5 123 330 seg146 434.8 628.6 24.5 123 331 seg147 393.3 628.6 24.5 123 332 seg148 351.8 628.6 24.5 123 333 seg149 310.3 628.6 24.5 123 334 seg150 268.8 628.6 24.5 123 335 seg151 227.3 628.6 24.5 123 336 seg152 185.8 628.6 24.5 123 337 seg153 144.3 628.6 24.5 123 338 seg154 102.8 628.6 24.5 123 339 seg155 61.3 628.6 24.5 123 340 seg156 19.8 628.6 24.5 123 341 seg157 -21.7 628.6 24.5 123 342 seg158 -63.2 628.6 24.5 123 343 seg159 -104.7 628.6 24.5 123 344 seg160 -146.2 628.6 24.5 123 345 seg161 -187.7 628.6 24.5 123 346 seg162 -229.2 628.6 24.5 123 347 seg163 -270.7 628.6 24.5 123 348 seg164 -312.2 628.6 24.5 123 349 seg165 -353.7 628.6 24.5 123 350 seg166 -395.2 628.6 24.5 123 351 seg167 -436.7 628.6 24.5 123 352 seg168 -478.2 628.6 24.5 123 353 seg169 -519.7 628.6 24.5 123 354 seg170 -561.2 628.6 24.5 123 355 seg171 -602.7 628.6 24.5 123 356 seg172 -644.2 628.6 24.5 123 357 seg173 -685.7 628.6 24.5 123 358 seg174 -727.2 628.6 24.5 123 359 seg175 -768.7 628.6 24.5 123 360 seg176 -810.2 628.6 24.5 123 361 seg177 -851.7 628.6 24.5 123 362 seg178 -893.2 628.6 24.5 123 363 seg179 -934.7 628.6 24.5 123 364 seg180 -976.2 628.6 24.5 123 365 seg181 -1017.7 628.6 24.5 123 366 seg182 -1059.2 628.6 24.5 123 367 seg183 -1100.7 628.6 24.5 123 368 seg184 -1142.2 628.6 24.5 123 369 seg185 -1183.7 628.6 24.5 123 370 seg186 -1225.2 628.6 24.5 123 371 seg187 -1266.7 628.6 24.5 123 372 seg188 -1308.2 628.6 24.5 123
u ltra c hip high-voltage mixed-signal ic ?1999~2003 64 es specifications # pad name x y w h 373 seg189 -1349.7 628.6 24.5 123 374 seg190 -1391.2 628.6 24.5 123 375 seg191 -1432.7 628.6 24.5 123 376 seg192 -1474.2 628.6 24.5 123 377 seg193 -1515.7 628.6 24.5 123 378 seg194 -1557.2 628.6 24.5 123 379 seg195 -1598.7 628.6 24.5 123 380 seg196 -1640.2 628.6 24.5 123 381 seg197 -1681.7 628.6 24.5 123 382 seg198 -1723.2 628.6 24.5 123 383 seg199 -1764.7 628.6 24.5 123 384 seg200 -1806.2 628.6 24.5 123 385 seg201 -1847.7 628.6 24.5 123 386 seg202 -1889.2 628.6 24.5 123 387 seg203 -1930.7 628.6 24.5 123 388 seg204 -1972.2 628.6 24.5 123 389 seg205 -2013.7 628.6 24.5 123 390 seg206 -2055.2 628.6 24.5 123 391 seg207 -2096.7 628.6 24.5 123 392 seg208 -2138.2 628.6 24.5 123 393 seg209 -2179.7 628.6 24.5 123 394 seg210 -2221.2 628.6 24.5 123 395 seg211 -2262.7 628.6 24.5 123 396 seg212 -2304.2 628.6 24.5 123 397 seg213 -2345.7 628.6 24.5 123 398 seg214 -2387.2 628.6 24.5 123 399 seg215 -2428.7 628.6 24.5 123 400 seg216 -2470.2 628.6 24.5 123 401 seg217 -2511.7 628.6 24.5 123 402 seg218 -2553.2 628.6 24.5 123 403 seg219 -2594.7 628.6 24.5 123 404 seg220 -2636.2 628.6 24.5 123 405 seg221 -2677.7 628.6 24.5 123 406 seg222 -2719.2 628.6 24.5 123 407 seg223 -2760.7 628.6 24.5 123 408 seg224 -2802.2 628.6 24.5 123 409 seg225 -2843.7 628.6 24.5 123 410 seg226 -2885.2 628.6 24.5 123 411 seg227 -2926.7 628.6 24.5 123 412 seg228 -2968.2 628.6 24.5 123 413 seg229 -3009.7 628.6 24.5 123 414 seg230 -3051.2 628.6 24.5 123 415 seg231 -3092.7 628.6 24.5 123 416 seg232 -3134.2 628.6 24.5 123 417 seg233 -3175.7 628.6 24.5 123 418 seg234 -3217.2 628.6 24.5 123 419 seg235 -3258.7 628.6 24.5 123 420 seg236 -3300.2 628.6 24.5 123 421 seg237 -3341.7 628.6 24.5 123 422 seg238 -3383.2 628.6 24.5 123 423 seg239 -3424.7 628.6 24.5 123 424 seg240 -3466.2 628.6 24.5 123 425 seg241 -3507.7 628.6 24.5 123 426 seg242 -3549.2 628.6 24.5 123 427 seg243 -3590.7 628.6 24.5 123 428 seg244 -3632.2 628.6 24.5 123 429 seg245 -3673.7 628.6 24.5 123 430 seg246 -3715.2 628.6 24.5 123 431 seg247 -3756.7 628.6 24.5 123 432 seg248 -3798.2 628.6 24.5 123 433 seg249 -3839.7 628.6 24.5 123 434 seg250 -3881.2 628.6 24.5 123 435 seg251 -3922.7 628.6 24.5 123 # pad name x y w h 436 seg252 -3964.2 628.6 24.5 123 437 seg253 -4005.7 628.6 24.5 123 438 seg254 -4047.2 628.6 24.5 123 439 seg255 -4088.7 628.6 24.5 123 440 seg256 -4130.2 628.6 24.5 123 441 seg257 -4171.7 628.6 24.5 123 442 seg258 -4213.2 628.6 24.5 123 443 seg259 -4254.7 628.6 24.5 123 444 seg260 -4296.2 628.6 24.5 123 445 seg261 -4337.7 628.6 24.5 123 446 seg262 -4379.2 628.6 24.5 123 447 seg263 -4420.7 628.6 24.5 123 448 seg264 -4462.2 628.6 24.5 123 449 seg265 -4503.7 628.6 24.5 123 450 seg266 -4545.2 628.6 24.5 123 451 seg267 -4586.7 628.6 24.5 123 452 seg268 -4628.2 628.6 24.5 123 453 seg269 -4669.7 628.6 24.5 123 454 seg270 -4711.2 628.6 24.5 123 455 seg271 -4752.7 628.6 24.5 123 456 seg272 -4794.2 628.6 24.5 123 457 seg273 -4835.7 628.6 24.5 123 458 seg274 -4877.2 628.6 24.5 123 459 seg275 -4918.7 628.6 24.5 123 460 seg276 -4960.2 628.6 24.5 123 461 seg277 -5001.7 628.6 24.5 123 462 seg278 -5043.2 628.6 24.5 123 463 seg279 -5084.7 628.6 24.5 123 464 seg280 -5126.2 628.6 24.5 123 465 seg281 -5167.7 628.6 24.5 123 466 seg282 -5209.2 628.6 24.5 123 467 seg283 -5250.7 628.6 24.5 123 468 seg284 -5292.2 628.6 24.5 123 469 seg285 -5333.7 628.6 24.5 123 470 seg286 -5375.2 628.6 24.5 123 471 seg287 -5416.7 628.6 24.5 123 472 seg288 -5458.2 628.6 24.5 123 473 seg289 -5499.7 628.6 24.5 123 474 seg290 -5541.2 628.6 24.5 123 475 seg291 -5582.7 628.6 24.5 123 476 seg292 -5624.2 628.6 24.5 123 477 seg293 -5665.7 628.6 24.5 123 478 seg294 -5707.2 628.6 24.5 123 479 seg295 -5748.7 628.6 24.5 123 480 seg296 -5790.2 628.6 24.5 123 481 seg297 -5831.7 628.6 24.5 123 482 seg298 -5873.2 628.6 24.5 123 483 seg299 -5914.7 628.6 24.5 123 484 seg300 -5956.2 628.6 24.5 123 485 seg301 -5997.7 628.6 24.5 123 486 seg302 -6039.2 628.6 24.5 123 487 seg303 -6080.7 628.6 24.5 123 488 seg304 -6122.2 628.6 24.5 123 489 seg305 -6163.7 628.6 24.5 123 490 seg306 -6205.2 628.6 24.5 123 491 seg307 -6246.7 628.6 24.5 123 492 seg308 -6288.2 628.6 24.5 123 493 seg309 -6329.7 628.6 24.5 123 494 seg310 -6371.2 628.6 24.5 123 495 seg311 -6412.7 628.6 24.5 123 496 seg312 -6454.2 628.6 24.5 123
uc1682 80x104rgb cstn controller-driver revision 0.6 65 t ray i nformation package code drawing no. general roughness unless otherwise dimension 2" ic tray type:h20-558*68-28(30) ultra chip inc. w angle n/a drawing detail see 10-21-02' date by drawn iris chen mm unit tolerance n/a specified approved 10-21-02' alvin chang 10-21-02' checked alvin chang sheet material scale size 1 of 1 a4 rev. a proj. n/a
u ltra c hip high-voltage mixed-signal ic ?1999~2003 66 es specifications cof i nformation unit shown from copper side solder resist metal(cu) polyimide 4 ic 3 2 1 4 projection uc1682 cof package drawing scale 1:1 u c 6 1 8 2 sht 1 of 2 f b rev c ltra u inc. hip 1 2 3 4 5 revise describtion dftg chk appvl date new version 10/24/2002 jack c l drawing no. title 1 2 a b c d 3 c 1 a b c d 4 b d 2 a 1 43 28.782 (cut line) 27.968 (alignment mark) p0.094x41=3.854 (w=0.047) 26 (alignment hole) 16.93 max (resin area) 4.98 max (resin area) 7.733 (ic center) 34.98 0.17 31.82 4.75 x 5 s.p. = 23.75 1.42(sq) 17 (cut line) 2 0.2 p0.9x28=25.2 (w=0.45) 28.782 (cut line) 4.5 (alignment hole) 2 c l 0.8 max. (include ic) 1 398 1 29 14.391 (ic center) 3.vbo- 4.vb1- 2.vlcd 1.nc 20.rst 12.tst4 11.vbias 10.id 9.vss 8.vdd2,3 7.vdd 6.vb0+ 5.vb1+ 19.cs1 18.cs0 17.cd 16.wr0 15.wr1 14.bm0 13.bm1 28.d7 27.d6 26.d5 25.d4 24.d3 23.d2 22.d1 21.do 29.nc p0.094x41=3.854 (w=0.047) p0.062x313=19.406, w=0.031 0.5 2.8 12.2 0.2 (s/r) 0.094 0.094 27.8 0.2 (s/r) 26.65 (pi opening) a b 398 1
uc1682 80x104rgb cstn controller-driver revision 0.6 67 detail "a" projection uc1682 cof package drawing scale 1:1 u c 6 1 8 2 sht 2 of 2 f b rev c ltra u inc. hip 1 2 3 4 5 revise describtion dftg chk appvl date new version 10/24/2002 jack drawing no. title 1 winding direction copper input polyimide reel 405 un-winding direction output base film copper solder resist plating 2 3 4 no. 1 material component list after olb 2 a b c d 3 c 1 a b c d 4 b d 2 a 1 43 unit shown from copper side 0.1 0.74 0.407 0.8 0.8 0.1 vb1+ vb0- vb1- 2 1 nc vlcd vb0+ vdd vss id vbias tst4 vdd2,3 bm1 cd wr1 wr0 bm0 cs0 cs1 d0 d1 d3 d4 d2 d7 rst d5 d6 uc1682b ic nc 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 seg 307 seg 306 com 4 com 2 nc 349 350 357 359 358 nc com 77 com 79 nc nc com 1 com 3 43 42 3 2 1 40 41 nc com 80 com 78 396 397 398 nc seg 1 44 356 351 352 354 355 353 seg 308 seg 309 seg 310 seg 311 seg 312 2- 1.1(pi) 2- 1.0 (cu hole) detail "b"
u ltra c hip high-voltage mixed-signal ic ?1999~2003 68 es specifications r evision h istory version contents date of rev. 0.0 preliminary specification jul. 10, 2003 0.1 new release jul. 24, 2003 0.6 figure 15 ?reference power-up sequence? is updated for otp. (section ?reset & power management?, page 46; ?power up? table, page 47.) aug. 11, 2003

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